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Design of a high-throughput low-power IS95 Viterbi decoder

Xun Liu, Marios C. Papaefthymiou
2002 Proceedings - Design Automation Conference  
Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages.  ...  The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption.  ...  MINIMIZING GLOBAL BUSES This section describes our operation packing scheme for global bus minimization.  ... 
doi:10.1145/513918.513988 dblp:conf/dac/LiuP02 fatcat:fcqcsxci7nb4dkjforfj5gptle

Design of a high-throughput low-power IS95 Viterbi decoder

Xun Liu, M.C. Papaefthymiou
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages.  ...  The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption.  ...  MINIMIZING GLOBAL BUSES This section describes our operation packing scheme for global bus minimization.  ... 
doi:10.1109/dac.2002.1012633 fatcat:thuxtml7ujb5hd76uoa4ok264y

Design of a high-throughput low-power IS95 Viterbi decoder

Xun Liu, Marios C. Papaefthymiou
2002 Proceedings - Design Automation Conference  
Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages.  ...  The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption.  ...  MINIMIZING GLOBAL BUSES This section describes our operation packing scheme for global bus minimization.  ... 
doi:10.1145/513987.513988 fatcat:ip2sr3geprc77hs26t7kl24me4

Testing NASA's 3D-stack MCM space flight computer

K. Sasidhar, L. Alkalai, A. Chatterjee
1998 IEEE Design & Test of Computers  
For example, the TMS line connected to an IC in the I/O MCM slice is the wired-OR of the TMS lines of test buses JTAG1 and JTAG2 in Figure 15 .  ...  Figure 14 .Figure 15 . 1415 Test scheme for 3D flight computer module. Redundant JTAG buses in the 3D MCM stack. Figure 16 . 16 Test structures in the processor slice.  ... 
doi:10.1109/54.706032 fatcat:3b263iit5rebvberk6dejaqraq

Design and verification of WISHBONE bus interface for System-on-Chip integration

Ayas Kanta Swain, KamalaKanta Mahapatra
2010 2010 Annual IEEE India Conference (INDICON)  
ACKNOWLEDGMENT This work was supported by Ministry of Communication and Information Technology (MCIT), Government of India. Also, CAD tools and boards used in this work are supported by MCIT.  ...  For implementing shared bus interconnection topology a multiplexor interconnections and non-multiplexed address and data buses are chosen.  ...  Fig. 2 shows the architecture of system design using WISHBONE shared bus interconnection scheme. It consists of four DMA Masters, four Memory Slaves, and SYSCON cores as described above.  ... 
doi:10.1109/indcon.2010.5712616 fatcat:slsph3fucjbdjb27jhwj74yfhi

On-FPGA Communication Architectures and Design Factors

Terrence T. Mak, Pete Sedcole, Peter K. Cheung, Wayne Luk
2006 2006 International Conference on Field Programmable Logic and Applications  
These platforms require high-performance on-chip communication architectures for efficient and reliable inter-processor communication.  ...  The recent development of Platform-FPGA or Field-Programmable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potential for immense computing  ...  For the surveyed architectures, shared buses and NoC architectures generally are designed with modularity abstraction.  ... 
doi:10.1109/fpl.2006.311209 dblp:conf/fpl/MakSCL06 fatcat:xmwjluwdpva4bnm2abhitvtvce

Synthesis of application-specific heterogeneous multiprocessor systems (abstract)

Shiv Prakash, Alice C. Parker
1992 SIGARCH Computer Architecture News  
Next we shall study the performance effects of various bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and their effect on the processor cycle time.  ...  This short note describes issues involved in the bypassing mechanism for a very long instruction word (VLIW) processor and its relation to the pipeline structure of the processor.  ...  The buses required for this scheme are longer than ones required for P = P2, because they have to cross the entire height of the register file.  ... 
doi:10.1145/146628.140538 fatcat:p6hrkpvy7zdtfcawrsrrolbiwi

A flexible datapath allocation method for architectural synthesis

Kyumyung Choi, Steven P. Levitan
1999 ACM Transactions on Design Automation of Electronic Systems  
topologies for interconnection architectures.  ...  The proposed method consists of a new binding model construction scheme and an optimization technique based on simulated annealing.  ...  First, we set a restriction for our target architecture to be a bit-sliced stack and a random topology interconnection.  ... 
doi:10.1145/323480.323486 fatcat:cyumbdrdavbmncskzomlwom6ve

Pipelining and bypassing in a VLIW processor

A. Abnous, N. Bagherzadeh
1994 IEEE Transactions on Parallel and Distributed Systems  
Next we shall study the performance effects of various bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and their effect on the processor cycle time.  ...  This short note describes issues involved in the bypassing mechanism for a very long instruction word (VLIW) processor and its relation to the pipeline structure of the processor.  ...  The buses required for this scheme are longer than ones required for P = P2, because they have to cross the entire height of the register file.  ... 
doi:10.1109/71.285612 fatcat:jrxjrviylfbvdicvhp6pnr2jmu

On-chip interconnect schemes for reconfigurable system-on-chip

Andy S. Lee, Neil W. Bergmann, Derek Abbott, Kamran Eshraghian, Charles A. Musca, Dimitris Pavlidis, Neil Weste
2004 Microelectronics: Design, Technology, and Packaging  
This paper motivates the need for such research and analyses current and proposed interconnect technologies for rSoC design.  ...  This projects aims to develop an interface logic generation methodology which can be used across different communications architectures (not just parallel buses).  ...  Architecture selection Our study of the different interconnection technologies has found that interconnect schemes can be divided into three main categories: serial schemes, parallel buses and communication-based  ... 
doi:10.1117/12.523334 fatcat:ywworo2ipvfgbggssxuedgj33q

Communication Architectures for Dynamically Reconfigurable FPGA Designs

Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hubner, Jurgen Becker
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
A set of parameters for the classification of the different communication architectures is presented and the pro and cons of each architecture are elaborated.  ...  This paper gives a survey of communication architectures which allow for dynamically exchangeable hardware modules.  ...  Additional area overhead is introduced by the arbiter, and the input-and output macros for one slot, so that in total 296 slices are required for the presented system.  ... 
doi:10.1109/ipdps.2007.370364 dblp:conf/ipps/PionteckAKMHB07 fatcat:ncpwwenguva4bo5ppr6lct3hqa

High-level synthesis under multi-cycle interconnect delay

Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi
2001 Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01  
We first define our distributed target architecture, which minimizes the effect of interconnect delay on clock cycle time.  ...  We incorporate the concept of multi-cycle interconnect delay into scheduling and binding process, to reduce the critical path length and therefore the system latency.  ...  In this architecture, we define two terms -Intra-FU cycle time (T INTRA ) for the computation and Inter-FU cycle time (T INTER ) for the communication -that are defined as T INTRA = T LOGIC + T R2FU  ... 
doi:10.1145/370155.370576 dblp:conf/aspdac/JeonKSC01 fatcat:q7ns3o6bbbcntevl7zunxghfpu

A partitioning scheme for optimizing interconnect power

R. Mehra, L.M. Guerra, J.M. Rabaey
1997 IEEE Journal of Solid-State Circuits  
An architecture-synthesis technique for the lowpower implementation of real-time applications is presented.  ...  This results in reduced usage of long high-capacitance buses, fewer accesses to multiplexors and buffers, and more compact layouts.  ...  Hendrickson and R. Leland of the Sandia National Laboratories for providing their implementation of the Lanczos method for calculating eigenvectors [18] . Ms.  ... 
doi:10.1109/4.557644 fatcat:donoslvzz5c5dgeie7jys3e7gi

Towards scalable, energy-efficient, bus-based on-chip networks

Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian
2010 HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture  
Thus, with the combination of all the above innovations, we extend the scalability of buses and believe that buses can be a viable and attractive option for future on-chip networks.  ...  It is expected that future on-chip networks for many-core processors will impose huge overheads in terms of energy, delay, complexity, verification effort, and area.  ...  We now describe the working and arbitration scheme for such a network.  ... 
doi:10.1109/hpca.2010.5416639 dblp:conf/hpca/UdipiMB10 fatcat:a6x4ppxwbvcdthupelph4mhu64

A scheduling algorithm for synthesis of bus-partitioned architectures

Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru
1995 Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC '95  
Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design.  ...  This paper presents a new approach for integrated scheduling and interconnect binding of bus-segmented data-paths.  ...  Acknowledgements The authors would like to acknowledge the support they received for this research from the Ministry of Education, Science and Culture of Japan under Grant No. A06780255.  ... 
doi:10.1145/224818.224837 dblp:conf/aspdac/MoshnyagaOT95 fatcat:4xnpynnjonckfhozn4w2cbwldm
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