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Page 1063 of IEEE Transactions on Computers Vol. 52, Issue 8 [page]

2003 IEEE Transactions on Computers  
The proposed design for testability approach is economical in delay, area, and pin overheads.  ...  inputs to simplify testing by augmenting a machine so that it contains the synchronizing sequence and the distinguishing sequence, through which an easily testable sequential machine can be designed.  ... 

Irredundant sequential machines via optimal logic synthesis

S. Devadas, H.-K.T. Ma, A.R. Newton, A. Sangiovanni-Vincentelli
1990 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Unlike previous Graph. truth table or by an interconnection of gates and flipsynthesis approaches to ensuring fuUy testable machines. there is flops.  ...  Previous approaches to producing fully and easily testable sequential circuits have involved the use of extra logic and constraints on state assignment and logic optimization.  ...  Complete Scan Design approach.  ... 
doi:10.1109/43.45852 fatcat:bvhosq2p3jgkvdphzvmmvyh5u4

Design for testability using register-transfer level partial scan selection

Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka
1995 Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC '95  
An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described.  ...  We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines.  ...  CONCLUSION In this paper we described an approach to design for testability at RTL.  ... 
doi:10.1145/224818.224900 dblp:conf/aspdac/MotoharaTHOTMM95 fatcat:eiiu23urkzfhzh3z7tfophxn4y

Easily testable PLA-based finite state machines

S. Devadas, H.-K.T. Ma
1990 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Previous approaches to synthesizing easily testable sequential machines have concentrated on the stuck-at fault model.  ...  Test generation and design-for-testability techniques for PLA structures have been active areas of research.  ...  and identification of all reduntest generation. dant faults was proposed in [20]. sequential circu~tr, design for testability has been Design-for-testability techniques (e.g. [11]) for PLAs vnonym for  ... 
doi:10.1109/43.55190 fatcat:j7oxfnsnnjefbhzhw7rw2rtx24

Constrained state assignment of easily testable FSMs

Mar�a J. Avedillo, Jos� M. Quintana, Jos� L. Huertas
1995 Journal of electronic testing  
We state sufficient conditions for faulty states to propagate to primary outputs in one clock cycle and use them to derive the constraints that must be imposed on the state assignment of the machine to  ...  We investigate the relationship between the state assignment of the sequential machine and the observability of a faulty internal state on the primary outputs for faults that result in unidirectional errors  ...  For each machine Table II depicts the number of product terms and size of combinational component with different design approaches: 1) synthesis without testability considerations; 2) results with  ... 
doi:10.1007/bf00993136 fatcat:q4hyugcsazblnbfmefpu2alm6u

Simplifying sequential circuit test generation

Meng-Lieh Sheu, Chung Len Lee
1994 IEEE Design & Test of Computers  
SEQUENTIAL TEST generation poses a difficult problem for circuits implemented from finite-state machines.  ...  We have developed a parity checker design-fortestability scheme that significantly enhances circuit testability, thus simplifying the testability problem.  ...  Acknowledgments The authors wish to express their gratitude for helpful comments from the reviewers.  ... 
doi:10.1109/mdt.1994.303845 fatcat:jsguvvufijbsrpdfkxp2szkf6u


M. A. Mіrosсhnyk, Y. V. Pakhomov, A. S. Shkil, E. N. Kulak, D. Y. Kucherenko
2018 Radìoelektronika, Ìnformatika, Upravlìnnâ  
The task of computer-aided design of testable control finite state machine on the basis of application of FSM' setting methods into given state is solved in the work.  ...  of finite state machine into an arbitrary state without the use of synchronizing sequences.  ...  During a functional approach to designing (analyzing) of digital devices which specified by the finite state machine > λ δ =< , , , , Y A X W , increasing the testability of an FSM is possible only by  ... 
doi:10.15588/1607-3274-2018-2-13 fatcat:rkwfygbdz5ezdd42uhsp6eecje

Nonscan design for testability for synchronous sequential circuits based on conflict resolution

Dong Xiang, Yi Xu, H. Fujiwara
2003 IEEE transactions on computers  
The proposed design for testability approach is economical in delay, area, and pin overheads.  ...  inputs to simplify testing by augmenting a machine so that it contains the synchronizing sequence and the distinguishing sequence, through which an easily testable sequential machine can be designed.  ... 
doi:10.1109/tc.2003.1223640 fatcat:djwklsjojbhj5igduj2cw6y5z4

TESTABLE: Testability-driven security and privacy testing for Web Applications

Luca Compagna, Giancarlo Pellegrino, Davide Balzarotti, Martin Johns, Angel Cuevas, Battista Biggio, Leyla Bilge, Fabian Yamaguchi, Matteo Meucci
2022 Zenodo  
the security and privacy risks of a program, i.e., the testability of the codebase (via the novel concept of "testability patterns") and the indicators for vulnerable behaviors.  ...  Motivated by the many security vulnerabilities and data breaches routinely reported on those applications, we initiated the EU TESTABLE research project to address the main challenges of building and maintaining  ...  An introduction to our approach, instantiated for the SAST domain, is discussed in Section 2.  ... 
doi:10.5281/zenodo.7068721 fatcat:zrelrpl7nnfhjl2dyutv4gabee

Testability of Dynamic Real-Time Systems: An Empirical Study of Constrained Execution Environment Implications

Birgitta Lindstr, Jeff Offutt, Sten F. Andler
2008 2008 International Conference on Software Testing, Verification, and Validation  
Using a constrained execution environment, we attempt to increase the testability of such systems. An initial step is to identify factors that affect testability.  ...  The results show that some of the factors, previously identified as possibly impacting testability, do not have an impact, while others do.  ...  Designing for resource adequacy is often expensive and infeasible when the environment is unpredictable. The alternative is to use an approach that includes dynamic, online scheduling.  ... 
doi:10.1109/icst.2008.21 dblp:conf/icst/LindstromOA08 fatcat:65o63fznvvb33ab2kprtqevcva

Self-checking design in Eastern Europe

S.J. Piestrak
1996 IEEE Design & Test of Computers  
9ais an example of a one-input (x,), three-output ly,, y2, y3} linear state machine with six delay elements, given by the following matrices: 9b gives the checking linear state machine Mk for M , designed  ...  One notable common restriction in all known selfchecking synchronous state machines (SSMs) is that faults on the clock lines do not occur.  ... 
doi:10.1109/54.485779 fatcat:ojjkpzvtifh5dlzrwnjnvlprz4

Firmware quality assurance

Helmut K. Berg, Prakash Rao, Bruce D. Shriver
1982 Proceedings of the June 7-10, 1982, national computer conference on - AFIPS '82  
The impact of advances and trends in very large-scale integration (VLSI) on the techniques and tools for firmware quality assurance is reviewed.  ...  The emphasis of the paper is on formal correctness proofs, firmware testing, and the automatic synthesis of microcode and associated hardware structures.  ...  Traditional methods of design for testability have taken the first approach.  ... 
doi:10.1145/1500774.1500776 dblp:conf/afips/BergRS82 fatcat:wg5ytjwyyjdhxa2qqbpxiq3zga

A synthesis for testability scheme for finite state machines using clock control

K.L. Einspahr, S.K. Mehta, S.C. Seth
1999 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
A new method is proposed for improving the testability of a finite state machine (FSM) during its synthesis.  ...  Theoretical results show that for a large class of FSM's, the testability improvements are comparable to those achievable by scan designs.  ...  Geng for his assistance with some of the experiments. They are also grateful to Dr. V. D. Agrawal for many helpful discussions.  ... 
doi:10.1109/43.811327 fatcat:rk5dmgteczburjatv6d2npbati

Synthesis of controllers for full testability of integrated datapath-controller pairs

Joan Carletta, Mehrdad Nourani, Christos Papachristou
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
Such an approach requires less test overhead than an approach that isolates datapath and controller from each other during test.  ...  A method for controller synthesis is outlined that results in a fully testable controller, so that full fault coverage of the controller can be achieved without any need for isolation during test.  ...  Conclusions This work presented an approach for the synthesis of finite state machine controllers that results in controllers that are fully testable even without separating the controller from its environment  ... 
doi:10.1145/307418.307505 fatcat:n5nfzhkg2zed5b44palbymdcou

Transient and Permanent Fault Injection in VHDL Description of Digital Circuits

Parag K. Lala
2012 Circuits and Systems  
The ability to evaluate the testability of digital circuits before they are actually implemented is critical for designing highly reliable systems.  ...  This feature enables designers to verify the fault detection capability of online as well as offline testable digital circuits for both permanent and transient faults, during the design stage of the circuits  ...  With predominately behavioral design approaches being used in system design especially in describing complex state machines, it is not possible to predict the structure of the circuit generated by the  ... 
doi:10.4236/cs.2012.32026 fatcat:q7jgfdixcfctbhznlbswv3w74q
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