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Instrumentation Set-up for Instruction Level Power Modeling [chapter]

S. Nikolaidis, N. Kavvadias, P. Neofotistos, K. Kosmatopoulos, T. Laopoulos, L. Bisdounis
2002 Lecture Notes in Computer Science  
Energy constraints form an important part of the design specification for processors running embedded applications.  ...  A methodology and the corresponding instrumentation setup for taking current measurements to create high quality instruction level power models, are discussed in this paper.  ...  A large number of embedded computing applications are power or energy critical, that is power constraints form an important part of the design specification [1] .  ... 
doi:10.1007/3-540-45716-x_8 fatcat:52qcnn5bsbdofjwz6vofjctmhi

Quality programmable vector processors for approximate computing

Swagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2013 Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-46  
CONTRIBUTIONS  Quality programmable processors An abstract model for programmable approximate processors  QUORA A quality programmable 1D/2D vector processor Requirements: • HW/SW interface  ...  Programmable accelerators (GPGPUs, MIC) / Vector processors Domain-specific accelerators - image, video … Algorithm- specific accelerators General purpose processors/ Application specific  ... 
doi:10.1145/2540708.2540710 dblp:conf/micro/VenkataramaniCCRR13 fatcat:av3icaigq5ak7ozwkuunwh2oxi

Measurement of current variations for the estimation of software-related power consumption

T. Laopoulos, P. Neofotistos, C.A. Kosmatopoulos, S. Nikolaidis
2003 IEEE Transactions on Instrumentation and Measurement  
behavior of single-chip processing systems for low-power applications.  ...  Accurate monitoring of the instantaneous variations of the power supply current provides the appropriate information for the estimation of the power consumption at different operating situations of the  ...  For each one of the instructions, a set of power factors are assigned considering two main cases: a) to determine a base power cost, proportional to the processor current consumption and to the corresponding  ... 
doi:10.1109/tim.2003.816837 fatcat:agw72hhhizgpzkth27bz62bu5y

RECONFIGURABLE FPGA BASED SOFT-CORE PROCESSOR FOR SIMD APPLICATIONS

Maheswari R, Pattabiraman V, Sharmila P
2017 Asian Journal of Pharmaceutical and Clinical Research  
processor improves image quality by doubling the frame rate up-to 60 fps (frames per second) with peak power consumption of 400mWatt.  ...  portable embedded SIMD based applications which need high performance at reduced power consumptions  ...  This paper performs an analysis of field programmable gate array (FPGA)-based high performance reconfigurable open reduced instruction set computer 1200 (ROR) soft-core processor for SIMD.  ... 
doi:10.22159/ajpcr.2017.v10s1.19632 fatcat:uu2crmcltvgdtparrdzwszig7u

Rapid processor customization for design optimization: A case study of ECG R-peak detection

Mladen Milosevic, Emil Jovanov, Aleksandar Milenkovic
2011 2011 IEEE Biomedical Circuits and Systems Conference (BioCAS)  
We introduce custom instructions to expedite wavelet processing used in an ECG R-peak detection application.  ...  We explore several instruction extensions and show that customized processor cores significantly reduce program execution time and energy requirements for this application.  ...  PROCESSOR CUSTOMIZATION Wearable devices for health monitoring are powered by batteries.  ... 
doi:10.1109/biocas.2011.6107764 fatcat:zyafrmvvurf5bggnvdqrhwpmbq

Verification of configurable processor cores

Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas
2000 Proceedings of the 37th conference on Design automation - DAC '00  
This paper presents a verification methodology for configurable processor cores.  ...  Coverage analysis provides an evaluation of how well a specific design has been exercised, of the breadth of the configuration space explored, and suggests improvements to the process.  ...  The authors are especially grateful to the entire hardware team for building this verification methodology and for their insightful comments on drafts of the paper.  ... 
doi:10.1145/337292.337527 dblp:conf/dac/Puig-MedinaEK00 fatcat:kpkv4qfykvcg7ncpi3upk6el6m

MAESTRO: Orchestrating predictive resource management in future multicore systems

Sangyeun Cho, Socrates Demetriades
2011 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)  
For better resource management, MAESTRO monitors the program execution environment (hardware/OS) and application behaviors, learns useful knowledge from collected information, annotates the results of  ...  In this position paper, we make a case for a novel framework called MAESTRO which predictively manages system resources in shared-memory parallel computing platforms built with advanced multicore processors  ...  Specifically, the following four types of monitoring support appear especially helpful: (1) fine-grained processor functional unit usage counters, (2) specific instruction tracking, (3) power meter, and  ... 
doi:10.1109/ahs.2011.5963917 dblp:conf/ahs/ChoD11 fatcat:7qfcxjpkdjd33lwzubornspiom

A new framework for power estimation of embedded systems

C. Talarico, J.W. Rozenblit, V. Malhotra, A. Stritter
2005 Computer  
A proposed modular framework for assessing power consumption of embedded systems early in the design cycle can be extended to any performance metric and uses a high level of abstraction, leading to a faster  ...  It uses this value and bus capacitance to compute power consumption. Peripherals. For a processor, the term "instruction" generally means an atomic action for programming the desired behavior.  ...  Processor. Our framework relies on an ISS to estimate the power the CPU consumes to execute the application software.  ... 
doi:10.1109/mc.2005.39 fatcat:a2uje35gifg7fk6qdsqhrxilt4

Energy Efficiency Aspects of the AMD Zen 2 Architecture [article]

Robert Schöne, Thomas Ilsche, Mario Bielert, Markus Velten, Markus Schmidl, Daniel Hackenberg
2021 arXiv   pre-print
However, performance in contemporary server processors is primarily limited by power and thermal constraints.  ...  monitoring capabilities and its limitations.  ...  We measured an update rate of 1 ms for RAPL by polling the MSRs via the msr kernel module, which meets the specification for Intel processors. A.  ... 
arXiv:2108.00808v1 fatcat:ipp6sels7nfr7g3ciak27bbskq

A survey of the RISC-V architecture software support

Benjamin W. Mezger, Douglas A. Santos, Luigi Dilillo, Cesar A. Zeferino, Douglas R. Melo
2022 IEEE Access  
RISC-V is a novel open instruction set architecture that supports multiple platforms while maintaining simplicity and reliability.  ...  Despite its novelty, the software support for RISC-V has been increasing in the last years, given that popular tool-chains and operating systems already have support for RISC-V.  ...  Quality of Results (QoR) threshold for a specific application.  ... 
doi:10.1109/access.2022.3174125 fatcat:smbyxselm5gjxlk4pqilzrxjli

Pangaea

Henry Wong, Hong Wang, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham Chinya, Ankur Khandelwal Groen, Hong Jiang
2008 Proceedings of the 17th international conference on Parallel architectures and compilation techniques - PACT '08  
We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU.  ...  On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores.  ...  In addition, we would like to thank the anonymous reviewers whose valuable feedback has helped the authors greatly improve the quality of this paper.  ... 
doi:10.1145/1454115.1454125 dblp:conf/IEEEpact/WongBSACWCGJW08 fatcat:p37zbpaobza7pngzkxogk37fyy

Application Specific Instruction Set DSP Processors [chapter]

Dake Liu, Jian Wang
2013 Handbook of Signal Processing Systems  
Publishers is an imprint of Elsevier Morgan Kaufmann Publishers is an imprint of Elsevier.  ...  Although this book was written mainly for ASIP (application-specific instruction set processor) or ASIC (application-specific integrated circuit) designers, it will also benefit software programmers who  ...  The instruction set must be general because the application is unknown, and the programmer's behavior is unknown. ASIP designers have to think about the application and cost first.  ... 
doi:10.1007/978-1-4614-6859-2_21 fatcat:osttotl7yrdr5binkjo44angky

Instruction Level Energy Modeling for Pipelined Processors [chapter]

S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas
2003 Lecture Notes in Computer Science  
This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose.  ...  A new method for creating instruction level energy models for pipelined processors is introduced.  ...  Conclusions High quality instruction level energy models can be derived for pipelined processors by monitoring the instantaneous current drawn by the processor at each clock cycle.  ... 
doi:10.1007/978-3-540-39762-5_34 fatcat:r7c7bzxwdzc2fbd5fnh6dfwwei

Web Based Monitoring System for Nuclear Plant
English

2015 International Journal of Research and Applications  
This paper presents the wireless sensor network and Monitoring of Atmosphere at nuclear Power Plant is the main agenda in this paper by using Wireless Sensor Network (WSN).  ...  In receiving side zigbee module is connected to a Ethernet which is used for updating the values in to web server database.  ...  The ARM family offers high performance for very low power consumption, and small size. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles.  ... 
doi:10.17812/ijra.2.7(59)2015 fatcat:iatk3puqrfcttdg4zjryrp4sha

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing [chapter]

Jeremy Constantin, Ahmed Dogan, Oskar Andersson, Pascal Meinerzhagen, Joachim Rodrigues, David Atienza, Andreas Burg
2013 IFIP Advances in Information and Communication Technology  
In this paper, we propose an application-specific instruction-set processor (ASIP) processor that has been optimized for CS data compression and for operation in the subthreshold (sub-VT) regime.  ...  Our results show that the proposed ASIP accomplishes 62× speed-up and 11.6× power savings with respect to a straightforward CS implementation running on the baseline low-power processor without instruction  ...  Application-specific instruction-set processors (ASIPs) can compensate for the performance degradation issue, since they are optimized for a specific application domain, providing increased efficiency  ... 
doi:10.1007/978-3-642-45073-0_5 fatcat:c7ecljhguncfdjg3gsunowktiy
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