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An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variation

Jungsoo Kim, Younghoon Lee, Sungjoo Yoo, Chong-Min Kyung
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
Kim, et al., "An analytic dynamic scaling of supply voltage and body bias based on parallelism-aware workload and runtime distribution," in IEEE TCAD, Vol. 28, No. 4, Apr. 2009. [BYUN] W.-H.  ...  Martin, et al., "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads," in Proc. ICCAD 2002. Frequency vs.  ... 
doi:10.1109/aspdac.2010.5419820 dblp:conf/aspdac/KimLYK10 fatcat:dzd2wul7rfd6dhtexj2vylpjha

2009 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 28

2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., and Gielen, G. G. E., Globally Reliable Variation-Aware Sizing Ko, H.  ...  ., +, TCAD Aug. 2009 1224-1236 An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution.  ...  ., +, TCAD Nov. 2009 1691-1704 An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution.  ... 
doi:10.1109/tcad.2009.2036802 fatcat:hxyu2mmrnzfnbi6qlt6bklkgku

Variation-aware dynamic voltage/frequency scaling

Sebastian Herbert, Diana Marculescu
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
Fine-grained dynamic voltage/frequency scaling (DVFS) is an important tool in managing the balance between power and performance in chip-multiprocessors.  ...  Two hardware DVFS control algorithms are considered and the gains enabled by incorporating variability-awareness are demonstrated on multithreaded commercial workloads.  ...  proposed and evaluated an implementation of dynamic body-biasing [27] . Tiwari et al.  ... 
doi:10.1109/hpca.2009.4798265 dblp:conf/hpca/HerbertM09 fatcat:zw6d25bcp5cdlotqqvw6gdx3gq

Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software

Abbas Rahimi, Luca Benini, Rajesh K. Gupta
2016 Proceedings of the IEEE  
| Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in modern microelectronic manufacturing processes with geometries in nanometer scales  ...  We then provide examples of real world resilient single-core and parallel architectures.  ...  Adaptive body biasing is one such runtime technique which carefully selects an appropriate body bias as an available parameter to tune the electrical circuit characteristics [37] , [38] .  ... 
doi:10.1109/jproc.2016.2518864 fatcat:sxrsu3excbdg5p7sk4iczz262y

DPCS

Mark Gottscho, Abbas BanaiyanMofrad, Nikil Dutt, Alex Nicolau, Puneet Gupta
2015 ACM Transactions on Architecture and Code Optimization (TACO)  
Based on this observation, we propose a simple and low-overhead FTVS cache architecture for power/capacity scaling.  ...  We observe on our 45nm test chips that the "fault inclusion property" can enable lightweight fault maps that support multiple runtime supply voltages.  ...  Variation-Aware Selection of Allowed Runtime Voltage Levels.  ... 
doi:10.1145/2792982 fatcat:wswxryw3nzehtahpdd5vlmuj2e

Dynamic thermal management via architectural adaptation

Ramkumar Jayaseelan, Tulika Mitra
2009 Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09  
., dynamic voltage or frequency scaling (DVFS), clock gating, fetch gating, etc.) are engaged to lower the temperature if it exceeds a threshold.  ...  Dynamic thermal management (DTM) techniques continuously monitor the on-chip processor temperature.  ...  We use linear scaling in Wattch to obtain the power consumption with a supply voltage of 1.4 Volt and a frequency of 3.6 GHz at 100 nm, which corresponds to the supply voltage and frequency of the Pentium  ... 
doi:10.1145/1629911.1630038 dblp:conf/dac/JayaseelanM09 fatcat:33f65ws4rvcsdjvbylysavd6qu

Power Efficiency for Variation-Tolerant Multicore Processors

James Donald, Margaret Martonosi
2006 ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design  
We first examine a simplified case of our model on a platform running independent multiprogrammed workloads consisting of all 26 of the SPEC 2000 benchmarks.  ...  This work introduces an analytical approach for ensuring timing reliability while meeting the appropriate performance and power demands in spite of process variation.  ...  We also thank Chris Sadler and the anonymous reviewers for their helpful comments. This work is supported in part by grants from NSF, Intel, SRC, and the C2S2/GSRC joint microarchitecture thrust.  ... 
doi:10.1109/lpe.2006.4271854 fatcat:spfo44njvre4rmhfe6urwzicdq

Power efficiency for variation-tolerant multicore processors

James Donald, Margaret Martonosi
2006 Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED '06  
We first examine a simplified case of our model on a platform running independent multiprogrammed workloads consisting of all 26 of the SPEC 2000 benchmarks.  ...  This work introduces an analytical approach for ensuring timing reliability while meeting the appropriate performance and power demands in spite of process variation.  ...  We also thank Chris Sadler and the anonymous reviewers for their helpful comments. This work is supported in part by grants from NSF, Intel, SRC, and the C2S2/GSRC joint microarchitecture thrust.  ... 
doi:10.1145/1165573.1165645 dblp:conf/islped/DonaldM06 fatcat:vfcos6qzwrciho4cgudgu6w3xa

Power reduction techniques for microprocessor systems

Vasanth Venkatachalam, Michael Franz
2005 ACM Computing Surveys  
These techniques may eventually allow computers to break through the "power wall" and achieve unprecedented levels of performance, versatility, and reliability.  ...  Power consumption is a major factor that limits the performance of computers. We survey the "state of the art" in techniques that reduce the total power consumed by a microprocessor system over time.  ...  To adjust the threshold voltage, adaptive body biasing applies a voltage to the transistor's body known as a body bias voltage ( Figure 6 ).  ... 
doi:10.1145/1108956.1108957 fatcat:3v56rcg7yrejffkqp64hev4exi

Technologies for Ultradynamic Voltage Scaling

A.P. Chandrakasan, D.C. Daly, D.F. Finchelstein, J. Kwong, Y.K. Ramadass, M.E. Sinangil, V. Sze, N. Verma
2010 Proceedings of the IEEE  
An added challenge is that many of these applications have dynamic workloads.  ...  First, we describe an H.264/AVC video decoder that efficiently scales between QCIF and 1080p resolutions, using a supply voltage varying from 0.5 V to 0.85 V.  ...  Acknowledgment The authors would like to acknowledge Dimitri Antoniadis, Yu Cao, Eric Wang, and Wei Zhao for help with predictive technology models.  ... 
doi:10.1109/jproc.2009.2033621 fatcat:ehsup4tsbfa67ccdre7wvt26yq

Addressing computational and networking constraints to enable video streaming from wireless appliances

S. Chandra, S. Dey
2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.  
In [75] , the authors propose a combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to maximize the energy savings.  ...  Some of the proposed techniques include adaptive body bias control and adaptive supply voltage scaling [21, 6] , dual threshold voltage based design [22, 23] , gate sizing [24] , repeater insertion  ...  These models are used along with Monte Carlo sampling to design the variation-aware set of voltages.  ... 
doi:10.1109/estmed.2005.1518064 dblp:conf/estimedia/ChandraD05 fatcat:3kjqqg4gkvaj7gnganjbm6q4pe

ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level

Fabian Oboril, Mehdi B. Tahoori
2012 IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)  
of the architecture on aging.  ...  Furthermore, we show a comprehensive investigation using ExtraTime of various clock and power gating strategies as well as aging-aware instruction scheduling policies as a case study to show the impact  ...  To name just a few, special NBTI-resilient circuits [1] , input vector control [15] , [38] , power gating [9] , [10] , adaptive body biasing [32] , dynamic voltage and frequency scaling (DVFS) [  ... 
doi:10.1109/dsn.2012.6263957 dblp:conf/dsn/OborilT12 fatcat:xkhwomhesjfhlka3hwsmm3iemu

Understanding and Improving the Latency of DRAM-Based Memory Systems [article]

Kevin K. Chang
2017 arXiv   pre-print
We also examine the critical relationship between supply voltage and latency in modern DRAM chips and develop new mechanisms that exploit this voltage-latency trade-off to improve energy efficiency.  ...  These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memory), which has been used as the physical substrate for main memory.  ...  Memory Voltage and Frequency Scaling One proposed approach to reducing memory energy consumption is to scale the voltage and/or the frequency of DRAM based on the observed memory channel utilization.  ... 
arXiv:1712.08304v1 fatcat:6y2nr2eowvb5fhr7km7azmkioe

An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques [chapter]

Ivan Ratković, Nikola Bežanić, Osman S. Ünsal, Adrian Cristal, Veljko Milutinović
2015 Advances in Computers  
Both computer architects and circuit designers intent to reduce power and energy (without a performance Advances in Computers, Volume 98 # 2015 Elsevier Inc.  ...  Power dissipation and energy consumption became the primary design constraint for almost all computer systems in the last 15 years.  ...  Dwarkadas, and M. L. Scott [24] "Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems," L. Yan, J. Luo, and N. K.  ... 
doi:10.1016/bs.adcom.2015.04.001 fatcat:5voowf7sizcpxaumb74nelc25a

A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors

Sparsh Mittal
2016 ACM Computing Surveys  
and parallel performance.  ...  To meet the needs of diverse range of workloads, asymmetric multicore processors (AMPs) have been proposed, which feature cores of different microarchitecture or ISAs.  ...  The cores of an AMP may have different supply voltages and frequencies which presents manufacturing challenges.  ... 
doi:10.1145/2856125 fatcat:3hda47vtl5fznfvbskwcm2cbo4
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