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Guest Editorial: From Uniprocessors to Multiprocessors: Advances in Real-Time Systems

Luis Almeida
2013 Real-time systems  
Real-time multiprocessor computing has been an active area of research for many years. For example, several real-time multiprocessor scheduling results are known for more than three decades.  ...  The real-time systems community in particular has been dedicating substantial attention to issues such as the definition of analysable task models that better adapt to parallel platforms, the scheduling  ...  three of these works present analytical techniques that extend from uniprocessors to multiprocessors, contributing to a consolidation of the analysis of real-time systems.  ... 
doi:10.1007/s11241-013-9185-1 fatcat:zo3fjnk575dqpbfytj6nkcqyc4

Hierarchical cache/bus architecture for shared memory multiprocessors

A. W. Wilson
1987 Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87  
Finally, an analytic model is used to explore systems too large to simulate (with available hardware).  ...  A new, large scale multiprocessor architecture is presented in this paper. The architecture consists of hierarchies of shared buses and caches.  ...  In order to rapidly explore a larger design space, analytic models of the hierarchical multiprocessor system were constructed.  ... 
doi:10.1145/30350.30378 dblp:conf/isca/Wilson87 fatcat:yyaqljc45fe7ncgymfmmjikf2e

Timed Petri Net Models of Shared-Memory Bus-Based Multiprocessors

Wlodek M. Zuberek
2018 Journal of Computer and Communications  
In shared-memory bus-based multiprocessors, when the number of processors grows, the processors spend an increasing amount of time waiting for access to the bus (and shared memory).  ...  execution level, and the developed models are used to study how the performance of processors changes with the number of processors in the system.  ...  For example, the model shown in Figure 1 has only 12 states, so its analytical solution (for different values of modeling parameters) can be easily obtained.  ... 
doi:10.4236/jcc.2018.610001 fatcat:geggsomgojdr5aev6h6mu3uv7y

An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor

Taecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho
2009 2009 IEEE Computer Society Annual Symposium on VLSI  
A key design issue for chip multiprocessors (CMPs) is how to exploit the finite chip area to get the best system throughput.  ...  This paper presents a simple and effective analytical model to study the trade-off of the core count and the cache capacity in a CMP under a finite die area constraint.  ...  Authors thank the anonymous reviewers for their constructive comments.  ... 
doi:10.1109/isvlsi.2009.27 dblp:conf/isvlsi/OhLLC09 fatcat:rh7gpzgfwrhhlnnbasyfxp5cx4

Performance Analysis of Shared-Memory Bus-Based Multiprocessors Using Timed Petri Nets [chapter]

Wlodek M. Zuberek
2018 Petri Nets in Science and Engineering  
This chapter uses timed Petri nets to model shared-memory bus-based multiprocessors at the instruction execution level and shows how the performance of processors and the system are affected by different  ...  In shared-memory bus-based multiprocessors, the number of processors is often limited by the (shared) bus; when the utilization of the bus approaches 100%, processors spend an increasing amount of time  ...  Shared-memory bus-based systems An outline of a shared-memory bus-based multiprocessor is shown in Figure 5 .  ... 
doi:10.5772/intechopen.75589 fatcat:d3ao5fctinhahohd3psnetvyke

Prefetching and multithreading performance in bus-based multiprocessors with Petri Nets [chapter]

Edward D. Moreno, Sergio T. Kofuji, Marcelo H. Cintra
1997 Lecture Notes in Computer Science  
We also intend to develop and analyse such techniques, using simple but useful analytical models that predict the performance benefits achievable on bus-based multiprocessors.  ...  memory system.  ...  Differently from previous work with analytical models, we have modeled in detail the behaviour of the bus and the memory system, and the contention for their access.  ... 
doi:10.1007/bfb0002846 fatcat:kuc4gfer55brvatbvec6kgc7cq

Structured evaluation of computer systems

G. Bockle, H. Hellwagner, R. Lepold, G. Sandweg, B. Schallenberger, R. Thudt, S. Wallstab
1996 Computer  
Evaluating how well a system will perform is difficult because it is seldom done systematically. An approach developed at Siemens makes decisions explicit and the process reproducible.  ...  This chart employs the analytical cache-modeling method. We must then adapt the load representation to the kind of model.  ...  WE HAVE USED THIS METHOD to evaluate mainly computer systems and communication systems design, including multiprocessor systems, a parallel file system, and an ATM network.  ... 
doi:10.1109/2.507631 fatcat:6eslmisexrfbzjfrwva4aokomm

Guest Editors' Introduction Performance Evaluation of Multiple Processor Systems

1983 IEEE transactions on computers  
modeling, and simultation.  ...  In particular, the trend towards multiple processor systems, covering the spectrum from the tightly coupled multiprocessor organizations to geographically distributed processors, poses many new problems  ...  An analytic, closed queueing network model is presented, and two ap-proximate solutions are proposed: a hierarchical decomposition of multiple processor systems, for system designers as well as method  ... 
doi:10.1109/tc.1983.1676118 fatcat:fa3tq7gkvfemrgad23xs4mjmqm

Page 862 of IEEE Transactions on Computers Vol. 52, Issue 7 [page]

2003 IEEE Transactions on Computers  
We study this performance impact through detailed simulation, analytical modeling, and experiments on a flexible DSM prototype, using a range of parallel applications.  ...  The question we address in this paper is how the performance characteristics of the network and controller affect how well the machines will run parallel programs written for cache-coherent multiprocessors  ... 

A Performance Model for Memory Bandwidth Constrained Applications on Graphics Engines

Lin Ma, Roger D. Chamberlain
2012 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors  
Here, we propose an analytic model that helps improve the understanding of the performance of memory-limited kernels that employ random memory access schemes, especially as impacted by cache and various  ...  The analytic model is first explored through the use of a synthetic micro-benchmark, which is then followed by an empirical validation using a pair of production applications used in computational biology  ...  CONCLUSIONS The paper has presented an analytical performance model that is well suited for memory-limited kernels.  ... 
doi:10.1109/asap.2012.19 dblp:conf/asap/MaC12 fatcat:2cz5jkcm6vdrhnjrn4nnbrcrqm

Analytical Model For a MultiprocessorWith Private Caches And Shared Memory

Angel Vassilev Nikolov
2008 International Journal of Computers Communications & Control  
We develop an analytical model of multiprocessor with private caches and shared memory and obtain the following results: the instantaneous state probabilities and the steady-state probabilities of the  ...  system.  ...  Analytical Model For a Multiprocessor With Private Caches And Shared Memory 173 using Laplace transform and discrete transform [4, 8] the above equations are transformed as follows Table 1 : 1 Analytical  ... 
doi:10.15837/ijccc.2008.2.2385 fatcat:uiv2b74tbzeotgaqpyff7woupi

A general performance analysis method for uniform memory architectures

Jong-Jeng Chen, Chiau-Shin Wang, Ching-Roung Chou
1993 BIT Numerical Mathematics  
The method is further extended to estimate the performance of multiprocessor system with caches. The approximation results are also shown to be remarkably good.  ...  The performance of a multiprocessor system greatly depends on the bandwidth of its memory architecture.  ...  Figure I shows a general model of multiprocessor system with UMA architecture, where the big rectangle box can be any type of those interconnections.  ... 
doi:10.1007/bf01990534 fatcat:sdzhc26chfbfvm7tsysjm3s2cm

Limits on the performance benefits of multithreading and prefetching

Beng-Hong Lim, Ricardo Bianchini
1996 Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems - SIGMETRICS '96  
This paper presents new analytical models of the performance benefits of multithreading and prefetching, and experimental nleasurements of parallel applications on the MIT Alewife multiprocessor.  ...  The two models show that prefetching has a significant advantage over multithreading for machines with low memory latencies and/or applications with high cache miss rates because a prefetch instruction  ...  These models attempt to account for the effect of multithreading on other system parameters such as cache and network behavior.  ... 
doi:10.1145/233013.233021 dblp:conf/sigmetrics/LimB96 fatcat:dtf7p3jlnfffxa4cswtqhpksbu

Performance evaluation of the slotted ring multiprocessor

L.A. Barroso, M. Dubois
1995 IEEE transactions on computers  
In this paper we evaluate the performance of the unidirectional slotted ring interconnection for small to medium scale shared memory systems, using a hybrid methodology of analytical models and trace-driven  ...  As microprocessor speeds continue to improve at a very fast rate the bandwidth requirements for system level interconnections in multiprocessors may eventually rule out the use of shared buses even for  ...  In this paper we evaluate the unidirectional slotted ring as an alternative to buses for cache-based multiprocessor systems with up to 64 processors and in the context of multitasking.  ... 
doi:10.1109/12.392846 fatcat:6edhssskgfdjbabrfeqdclcqvu

Implementation of data cache block (DCB) in shared processor using field-programmable gate array (FPGA)

R Karthick, P Meenalochini
2020 Journal of the National Science Foundation of Sri Lanka  
The proposed work is used to minimize power consumption through an inverter amplifi er and a shared processor is used to reduce the system cost and increase performance.  ...  This research deals with a novel dynamic reconfi gurable multiprocessor technique combined with a System-On-Chip (SOC) and provides continuous transition activities in a digital environment.  ...  Every additional degree of cache will in general be greater and enhanced in an unexpected way.  ... 
doi:10.4038/jnsfsr.v48i4.10340 fatcat:qtgmocfgabafrne6atz7hjvrfe
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