A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Filters
A fault analysis method for synchronous sequential circuits
1990
Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90
Preserved Fulltext
For this reason, a fault analysis method capable of dealing with multiple faults is required. ...
of the set { f j s o ,~} ,
where ffis fault free, SO is
stuck-at4, and SI is stuck-at-1. ...
doi:10.1145/123186.123455
dblp:conf/dac/KuoLW90
fatcat:am7qncfwazglbjh5rm2ldlzke4
Defect Diagnosis of Digital Circuits Using Surrogate Faults
[chapter]
2013
Communications in Computer and Information Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2016; you can also visit the original URL.
The file type is application/pdf.
Although multiple stuck-at faults are used as an illustrative example of non-classical faults, proposed algorithms are applicable to any other type of fault. ...
Classical single stuck-at faults are analyzed as surrogates for any non-classical fault that may have caused an observed failure. ...
An utmost efficiency of the diagnosis algorithm can be expected from higher diagnostic capability test pattern set than from just the detection test pattern set. ...
doi:10.1007/978-3-642-42024-5_44
fatcat:b2asywgw4rdujbzk4pdd5uqo64
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
2008
IEICE transactions on information and systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
The proposed method deduces both the fault model and the fault location based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with ...
To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing test patterns. ...
Phase
1: We perform
single
stuck-at
fault
simulation
with
the set of failing
test patterns
to count
0(1)
detection
times
for the single
stuck-at
0(1)
fault
at each
line. ...
doi:10.1093/ietisy/e91-d.3.675
fatcat:2ywdh7k4xffp3erxnpjtrn3aze
OR-Bridging Fault Identification and Diagnosis for Exclusive-OR Sum of Products Reed-Muller Canonical Circuits
2011
Journal of Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2011; you can also visit the original URL.
The file type is application/pdf.
Problem statement: The faults in digital circuit can be classified broadly as single stuck-atfaults, multiple stuck-ay-faults, stuck-open faults, stuck-on faults, path delay faults, transient faults. ...
In this study a testable circuit with a small test set for detection and diagnosis of OR-bridging type fault in Reed-Muller canonical Exclusive-OR Sum of Products logic circuits, independent of the function ...
Zhongliang (2002) demonstrated that the single stuck-at fault detection can be achieved with only n+5 test vectors. ...
doi:10.3844/jcssp.2011.744.748
fatcat:v6bav7ywonf6fpi6zt6lwpsiry
Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools
2014
Journal of electronic testing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
usable by a conventional single stuck-at fault test pattern generator. ...
First, the detection of a transition delay fault or the diagnosis of a fault pair can be modeled in only one instead of two or four time-frames of the CUT. ...
An ATPG model for exclusive test generation for stuck-at faults transforms the problem to that of multiple-fault detection [2] . ...
doi:10.1007/s10836-014-5490-4
fatcat:pvjhivdrjzc5hiqt3wgzq4jtsi
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis
2011
2011 Sixteenth IEEE European Test Symposium
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2015; you can also visit the original URL.
The file type is application/pdf.
Online error detection techniques, including logic implication-based checker hardware, are capable of detecting at least some of these errors as they occur. ...
We will then utilize this information to select highly efficient test sets that can be used to effectively test the identified suspect locations in both the failing core and in other identical cores in ...
TABLE I NUMBER I OF STUCK-AT FAULTS DETECTED BY EACH IMPLICATION. ...
doi:10.1109/ets.2011.59
dblp:conf/ets/AlvesSIDNB11
fatcat:syecmkkrvjfhfkmvsizuwdpmga
Experimental Validation of a Resilient Electronic Logic Design with Autonomous Fault Discrimination/Masking
2015
Procedia CIRP
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The traditional logic layout is modified to include fault detection and reporting at an extremely fine-grained design level with 2x overhead as opposed to the traditional 4x overhead. ...
The test procedure is shown to be extensible towards more complex logic unit designs and for evaluation of multiple simultaneous faults. ...
Acknowledgements This work was carried out with the support of the EPSRC Innovative Centre for Through-life Engineering Services [EP/I033246/1]. ...
doi:10.1016/j.procir.2015.08.027
fatcat:psjoybzbgbbrnmwd4tzwpf6gl4
Detection of Faults in Programmable Logic Arrays
1979
IEEE transactions on computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
From 1961 until 1966, he worked for English _ l El Electric Computers at Kidgrove, England, first as a student apprentice and then as a data processing engineer. ...
The author would also like to thank N. Godiwala for several interesting discussions during the early stages of this research. ...
ACKNOWLEDGMENT The author would like to thank Prof. C. R. Kime and Prof. D. L. Dietmeyer for their careful reading ofthe manuscript and their many helpful suggestions. ...
doi:10.1109/tc.1979.1675264
fatcat:nyn6zcm6nfh27gugf3iumhjr5a
Net diagnosis using stuck-at and transition fault models
2012
2012 IEEE 30th VLSI Test Symposium (VTS)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
In this thesis, a procedure of diagnosing multiple net-faults is proposed. Many previous studies on fault diagnosis mainly focused on single failures. However, Vishwani D. Agrawal, the James J. ...
Diagnosis is the procedure used when circuit verification fails. Determining the cause of the failure and finding the possible defect locations are included in diagnosis. ...
At this stage, we want to reduce the influence of any lack of diagnostic capabilities in the test set. ...
doi:10.1109/vts.2012.6231106
dblp:conf/vts/ZhaoA12
fatcat:cbnggxfzlrautlkmfxlx5q3dyi
High-frequency, at-speed scan testing
2003
IEEE Design & Test of Computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2008; you can also visit the original URL.
The file type is application/pdf.
They present techniques for optimizing ATPG across multiple clock domains and propose methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite. ...
At-speed scan testing has demonstrated many successes in industry. One key feature is its ability to use on-chip clock for accurate timing in the application of test vectors in a tester. ...
Benware of LSI Logic regarding efficient merging of transition and stuck-at pattern sets. ...
doi:10.1109/mdt.2003.1232252
fatcat:qe5gwnwxjzftldugqyocau5kme
Testable Designs of Toffoli Fredkin Reversible Circuits
[article]
2021
arXiv
pre-print
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
Application of testing strategies to the logic circuits is a necessity that guarantees their true functioning where the researchers are at par with solutions for the upcoming challenges and agreements ...
Reversible logic is one of the alternatives that have capabilities to mitigate this dissipation by preventing the loss of bits. ...
Jimson Mathew, Associate Professor and Head, Department of Computer Science & Engineering, IIT Patna, for his excellencies during the final defense of work. . ...
arXiv:2108.07448v1
fatcat:7ukyd54yq5gqnav4ywdzmaijvi
Algorithm level recomputing using allocation diversity: a register transfer level approach to time redundancy-based concurrent error detection
2002
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2010; you can also visit the original URL.
The file type is application/pdf.
In this paper, the authors propose an algorithm-level time redundancy-based concurrent error detection (CED) scheme against permanent and transient faults by exploiting the hardware allocation diversity ...
at the register transfer level. ...
The types of faults we analyzed here are single stuck-at-1 fault, two nonadjacent stuck-at-1 faults, and two adjacent stuck-at-1 faults. ...
doi:10.1109/tcad.2002.801110
fatcat:tq6iahfqwbccfir4pqtqjuz7re
Concurrent test for digital linear systems
2001
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Error-detection capabilities of the scheme proposed in this work are analyzed and conditions on the implementation for achieving complete fault coverage are outlined. ...
Invariant-based concurrent test schemes can provide economical solutions to the problem of concurrent error detection. ...
During verification of the proposed scheme, a single stuck-at fault model is utilized. ...
doi:10.1109/43.945308
fatcat:xiu7onetyvdrhal4jvjouecj44
Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths
2003
IEEE Transactions on Reliability
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2010; you can also visit the original URL.
The file type is application/pdf.
Although algorithm level re-computing techniques can trade-off the fault detection capability vs. time overhead of a Concurrent Error Detection (CED) scheme, they result in 100% time overhead when the ...
strongest CED capability is achieved. ...
We considered single stuck-at-1 fault, two nonadjacent stuck-at-1 faults, and two adjacent stuck-at-1 faults; and combined the probabilities of not detecting these faults into one set (assuming ). ...
doi:10.1109/tr.2003.821942
fatcat:mwguvrlng5fjjewae53l5275aa
Alpha 21164 manufacturing test development and coverage analysis
1998
IEEE Design & Test of Computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2004; you can also visit the original URL.
The file type is application/pdf.
Acknowledgments We extend our sincere gratitude to the following people for their numerous contributions and consistent support: Dilip Bhavsar, Dave George, Bill Grundmann, Michael Kantrowitz, John Kapp ...
Evaluating vector set coverage Once we developed the initial vector set, we selected the classical single stuck-at-fault model to evaluate its coverage. ...
For three of the functional partitions, a single architectural verification test or a generic pseudorandom test sequence reached minimum 75% single stuck-at-fault coverage. ...
doi:10.1109/54.706040
fatcat:ghjjsetebrcxdkkxvgo6dng7ji
« Previous
Showing results 1 — 15 out of 8,869 results