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Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks
[chapter]
1999
Lecture Notes in Computer Science
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Both methods derive strong delay-verification test sets. ...
other path can be calculated from the propagation delays along the selected paths, b) all the selected paths are tested by using 2(3log 2 n+1) test vector pairs. ...
We have shown that the second method can alternatively be used to derive the maximum speed of the CUT. ...
doi:10.1007/3-540-48254-7_19
fatcat:wtwslgpdzvh7xdd6lpkv3u4wwm
Path delay fault testing of ICs with embedded intellectual property blocks
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
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used for path delay fault testing of the IC. ...
We show that the testing of the IC for path delay faults can be reduced to the testing of each block. Intellectual Property (IP) blocks are treated as black boxes. ...
We have shown that, using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the IC, the path delay fault testing of the IC is reduced to the path ...
doi:10.1145/307418.307468
fatcat:4xeosmhxhzdv3kknjxfm52fffi
Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling
2018
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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To overcome those limitations, in this paper we propose an alternative solution using transition fault test patterns, which is able to eliminate the need for PMBs, while improving the accuracy of voltage ...
The paper shows, using simulation of ISCAS'99 benchmarks with 28nm FD-SOI library, that AVS using transition fault testing (TF-based AVS) results in an error as low as 5.33%. ...
Authors of [8] propose an efficient technique for post manufacturing test set generation by determining only 10% representative paths and estimating the delays of other paths by statistical delay prediction ...
doi:10.23919/date.2018.8342022
dblp:conf/date/ZandrahimiDCA18
fatcat:bkr3fof2nvgxldsddi3ufpsbyy
Operations on Multiple Transition Faults without Enumeration
2016
MATEC Web of Conferences
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The multiple transition fault model has been used to represent alternative defective gate combinations in the circuit. ...
Furthermore, important operations for identifying the location of failures are implemented without fault enumeration. ...
Figure 3 shows an example of MTF generation using the deductive method. Let a test vector be T = {01, 11}. ...
doi:10.1051/matecconf/20167601012
fatcat:irbzklb4pvaktl7d3alij7uory
Static verification of test vectors for IR drop failure
2003
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
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ATPG tools generate test vectors assuming zero delay model for logic gates. ...
impacting path delays. ...
Sridhar, and Suravi Bhowmick for their helpful comments in the early stages of this work. ...
doi:10.1109/iccad.2003.159762
fatcat:4g732uhzqvfztmipooghbf2ngu
Software-based delay fault testing of processor cores
2003
Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-03
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This approach uses instruction set architecture, RT level description along with gate level netlist for test generation. ...
This paper presents a software-based self-testing methodology for delay fault testing. Delay faults will affect the circuit functionality only when it can be activated in functional mode. ...
Conclusion This paper, presented a systematic approach for delay fault testing using processor instruction set. ...
doi:10.1109/ats.2003.1250785
dblp:conf/ats/SinghISF03
fatcat:oak6pj2nqvgzhjoj22m3lnludu
Reconfigurable Scan Architecture for High Diagnostic Resolution
2021
IEEE Access
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An N-way scan architecture using one N:1 multiplexer per cell was proposed [28] to further improve the diagnostic resolution for the multiple faults. ...
The number of signal combinations that can be generated for multiplexer control signals is 2 . It becomes the total number of diagnosis path sets available for the tests. ...
doi:10.1109/access.2021.3108429
fatcat:fvfqn52a35cbznekhky5jap56i
Fast identification of robust dependent path delay faults
1995
Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95
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| Recently, it has been shown in [1] and [2] that in order to verify the correct timing of a manufactured circuit not all of its paths need to be considered for delay testing. ...
In addition, we consider the computational problem of identifying large sets of such not-necessary-to-test paths. ...
Saldanha for their support and helpful discussions. In addition, we thank R.K. Brayton, W.K. Lam, A. Saldanha, and A.L. Sangiovanni-Vincentelli for providing their RD-set identication program. ...
doi:10.1145/217474.217517
dblp:conf/dac/SparmannLCR95
fatcat:rjups4ebsnhhxi5s2e5frrpcm4
Computation of floating mode delay in combinational circuits: theory and algorithms
1993
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This algorithm uses conventional stuck-at-fault testing techniques to arrive at a delay computation method that is both correct and computationally practical, even for particularly difficult circuits. ...
We introduce the notion of static cosensitization of paths which leads us to necessary and sufficient conditions for determining the truth or falsity of a single path, or a set of paths. ...
This fault may then be tested using classic testing strategies. ...
doi:10.1109/43.251155
fatcat:3h6o3bek3vdsjivx775dx6wrqu
Low-power scan design using first-level supply gating
2005
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay and power overhead compared to existing methods, which use gating logic at the output of scan ...
We implement the masking effect by inserting an extra supply gating transistor in the VDD to GND path for the first level gates at the outputs of the scan flip-flops. ...
%improvement = 100 * (ov N OR − ov F LS )/ov N OR (2) Larger-sized gating transistors for gates in the critical path can be used to further reduce the delay penalty. ...
doi:10.1109/tvlsi.2004.842885
fatcat:hwq2k4rh2ff75ggmpo736up3ji
Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design
2010
IEEE Transactions on Instrumentation and Measurement
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The clockless wave pipeline represents an alternative to a traditional pipeline scheme; it requires an innovative computing model that is readily suitable for high-throughput computing by heterogeneous ...
A clockless-induced datawave fault model is proposed for clockless fault-tolerant design. ...
Intrawave Fault and Yield The path delay of a circuit with fabrication variations can be modeled using an interval, instead of a single value. ...
doi:10.1109/tim.2009.2030917
fatcat:frrcdew6sbfszmxxfghinvopyq
Layout driven logic synthesis for FPGAs
1994
Proceedings of the 31st annual conference on Design automation conference - DAC '94
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Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30%-50% of wires have alternative wires. ...
Allowing the logic blocks to have alternative functions also increases the flexibility of routing. The redundancy addition and removal techniques are used to identify such alternative wires. ...
For an external target wire, we can obtain a set of multiple-wire alternatives using the approach described earlier. In the following, we discuss the cost of an alternative wire. ...
doi:10.1145/196244.196388
dblp:conf/dac/ChangCWM94
fatcat:h4e5brsjbjc2hiimfbfd5qarli
Instruction-level DFT for testing processor and IP cores in system-on-a-chip
2001
Proceedings of the 38th conference on Design automation - DAC '01
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The experimental results show that with the added test instructions, a complete fault coverage for testable path delay faults can be achieved with a greater than 20% reduction in the program size and the ...
This paper discusses a method of identifying effective test instructions which could result in highest benefits with low area/performance overhead. ...
Then, a constrained structual gate-level ATPG (for stuck-at or delay faults) is used to generate deterministic tests for a target fault. ...
doi:10.1145/378239.378282
dblp:conf/dac/LaiC01
fatcat:jcqs5a6xp5gqnia7x54ooddz2m
Design a Low Power Built in SelfTest BIST Architecture for Fast Multiplier and Optimize in Terms of Real Time Functionality
2015
International Journal on Recent and Innovation Trends in Computing and Communication
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In this work, I have implemented 4bit * 4bit Multiplier with many test pattern generators (TPG) alternative. A BIST TPG Architecture was use of 6 bit counter. ...
Reduction of power dissipation achieved by properly assigning the TPG outputs to the multiplier inputs, significantly reducing the test set length, suitable TPG built of a 6-bit counter Keywords-BIST(Built ...
afault simulator along with a test set compression program.The result that would be obtained by this method wouldbe an optimal test set in terms of its cardinality but totallyinappropriate for implementation ...
doi:10.17762/ijritcc2321-8169.1503178
fatcat:xnhhualycbbofideawmyvckpve
Effectiveness of Software Metrics for Object-oriented System
2012
Procedia Technology - Elsevier
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Measurement is a buzzword applied to each and every field of engineering for the development of hardware or firmware products, and software engineering is nowhere an exception. ...
The metric values are evaluated for a real life application, which helps us to know the complexity and the reliability of the ATM software. ...
Hence cyclomatic complexity is one of the most suitable metric for generation of test cases for both feasible and non-feasible paths. CK metrics are the best indicators of fault proneness. ...
doi:10.1016/j.protcy.2012.10.050
fatcat:256wxg7oqrdq3fh32khqiiscle
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