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Switch-level simulation using dynamic graph algorithms
1991
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The main result of this paper is the development of an algorithm for switch-level simulation based on this incremental-updating technique using only local information. ...
A new model for MOS transistors suitable for logic simulation of VLSI circuits is presented, based on the concept of a dynamically directed switch (DDS). ...
Switch-Level Simulation Using Dynamic Graph Algorithms
Dan Adler Abstract-A new model for MOS transistors suitable for logic simulation of VLSI circuits is presented, based on the concept of a dynamically ...
doi:10.1109/43.67788
fatcat:tn6l3etjbbfa3azsocdzmdncmq
A Hardware Architecture for Switch-Level Simulation
1985
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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BRYANT, MEMBER, IEEE Abstract-The Mossim Simulation Engine (MSE) is a hardware ac celerator for performing switch-level simulation of MOS VLSI circuits [I], [2]. ...
A Hardware Architecture for Switch-Level Simulation ...
doi:10.1109/tcad.1985.1270120
fatcat:pclvgk6zqzcrtkfsdf42pn5d44
Limitations of switch level analysis for bridging faults
1989
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Switch level models are widely used for fault analysis of MOS digital circuits. ...
Switch level analysis (SLA) provides significantly more accurate results compared to the gate level models and also avoids the complexities of circuit level analysis. ...
The authors are thankful to the reviewers for their numerous suggestions and to Prof. C. W. Wilmsen of Colorado State University for his comments. ...
doi:10.1109/43.31538
fatcat:35jmvhvwerczvbac2qomxtcluu
Verity—A formal verification program for custom CMOS circuits
1995
IBM Journal of Research and Development
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performed at the RTL level. ...
In this paper we discuss Verity, a formal verification program for symbolically proving the equivalence between a high-level design specification and a MOS transistor-level implementation. ...
Acknowledgements The authors would like to thank Florian Krohm at the IBM Thomas J. ...
doi:10.1147/rd.391.0149
fatcat:7qjdn6i6ovcebfwd7cxa54zham
The complexity of fault detection in MOS VLSI circuits
1990
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The implications of these complexity results on practical transistor-level test generation tools are discussed. ...
This leads to a linear-time algorithm for CMOS logic gates which tests for robustness and, if possible, derives a robust test pair from a possibly non-robust pair. ...
Nevertheless, it is important to know whether polynomial-time algorithms for these problems, for general MOS circuits, exist or not. ...
doi:10.1109/43.59075
fatcat:gou3wkyvyvfdpcqnitavfewozi
An automated method for test model generation from switch level circuits
2003
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC
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This paper presents an automated flow for creating gate level test models from circuits at the switch level. ...
The proposed flow utilizes Motorola's Switch Level Verification (SLV) tool, which employs detailed switch level analysis to model the behavior of MOS transistors and represent them at a higher level of ...
The authors would like to thank Bruce Jilek and George Joos from the Somerset Design Center for their contributions to the development and beta testing of the SLV/ATPG flow in a real design environment ...
doi:10.1145/1119772.1119943
dblp:conf/aspdac/McDougallPJZZPA03
fatcat:7kkax2ycnffrpcsquv4tl7prtq
Digital MOS circuit partitioning with symbolic modeling
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
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Other applications of derived netlists cover switch-level simulation acceleration and test generation tool enhancement. ...
This paper presents a method to automatically recognize and model single and multi-output logic gates out of a switch-level network, even for irregular transistor structures. ...
Original circuits are described at the gate level and they have been flattened to the transistor level and reorganized into CCRs later with the help of the partitioning algorithm. ...
doi:10.1145/307418.307552
fatcat:r7ous7m6ezfqfk2voz4eeyucw4
A CMOS general-purpose sampled-data analog processing element
2000
IEEE transactions on circuits and systems - 2, Analog and digital signal processing
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The AP circuits operate with a 3.3-V power supply voltage and were tested, performing various algorithms, using a laboratory data generator as an external controller.
B. ...
For example, an AP intended for general-purpose signal filtering applications could use SI circuits of greater complexity, but much reduced errors [15] . ...
In an effort to eradicate shortcomings, Liu et al. proposed a third approach, which uses the current-mode square root and squarer circuits based on the square-law characteristics of MOS transistors operated ...
doi:10.1109/82.842115
fatcat:u7uawpoqqfamti5epl2jducqsq
CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices
2001
IEEE Journal of Solid-State Circuits
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The radix-2 SDFA circuit, based on two-peak negative-differential-resistance (NDR) devices, has been implemented using MOS-NDR, a new prototyping technique for circuits that combine MOS transistors and ...
intended for very compact designs capable of operating at extremely high speeds. ...
Therefore, the capacitance at the gate of M3 should be charged to a voltage level V a = V DD ;V T , and the switching delay is proportional to this voltage level. ...
doi:10.1109/4.924855
fatcat:44m3xxigyfc4npjkfbdkoososm
Adoption of fuzzy fractional order theory under Reco-Mo algorithm in data analysis of optical circuit switches
2020
Alexandria Engineering Journal
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In order to analyze the optimization value of Reco-Mo based on fuzzy fractional order theory for data analysis of optical circuit switches, first, the co-flow scheduling strategy is expounded. ...
circuit switches in data centers in the future. ...
Therefore, the Reco-Mo algorithm based on fuzzy fractional order for data analysis optimization of optical circuit switches is designed, and E-FWO algorithm and E-SCFE algorithm are introduced to conduct ...
doi:10.1016/j.aej.2020.06.033
fatcat:qlq6ls5bnzh7hohog5asowu32a
Logic synthesis for large pass transistor circuits
1997
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97
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In this work, we motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. ...
We also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. ...
Acknowledgments The authors would like to thank Prof. Takayasu Sakurai and Ravi Gunturi for useful discussions on this work. ...
doi:10.1109/iccad.1997.643609
dblp:conf/iccad/BuchNNS97
fatcat:tmhb5warxrf3zjwanxuno4yqsm
Boolean Analysis of MOS Circuits
1987
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The switch-level model represents a digital metal-oxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. ...
The analysis can serve as the basis of e cient programs for a variety o f l o g i c design tasks, including: logic simulation (on both conventional and special purpose computers), fault simulation, test ...
Similarly, automatic test pattern generation for switch-level circuits has not yet reached the success achieved for logic gate circuits. ...
doi:10.1109/tcad.1987.1270310
fatcat:hlzeppihwncrbdzwkz4rqzku5y
Optimization of Power Consumption in VLSI Circuit
2014
IOSR Journal of Electrical and Electronics Engineering
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Power consumption in VLSI circuit is data dependent. In this paper different design methods are tested to optimize the power. ...
It is found that algorithm based design reduces gate switching activity that results reduction of power in multiplier circuit. ...
A method is to compute the slack at each gate in the circuit, where the slack of a gate corresponds to how much the gate can be slowed down without affecting the critical delay of the circuit. ...
doi:10.9790/1676-09236266
fatcat:u6uz5kctbngvfig7wisv4trmju
A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system
2017
IEICE Electronics Express
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To achieve fast-transient time, a VSSa generator and a coarsefine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm 2 . ...
The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5 mA to 120 mA, and the step-down time is 0.1 us at 1.2 V of supply voltage. ...
Acknowledgments This work was supported by the Brain Korea 21 Plus Project in 2017. ...
doi:10.1587/elex.14.20170461
fatcat:l2uwl47qabbltn3xqm5hroh4t4
Design of Microgrid Simulation System
2019
IOP Conference Series: Materials Science and Engineering
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For reasonable deal with the relationship between the public power grid and distributed generation, this design by micro grid simulation system as an object, mainly studies the design method of grid inverter ...
, completed the grid inverter hardware system and control system design, and on the basis of the above work, the micro grid simulation system is designed by simulation analysis and experimental verification.Simulation ...
When the PWM signal changes, IR2104 also changes the output level. At this time, the MOS tube at the low end of the chip is off and the MOS tube at the high end is on. ...
doi:10.1088/1757-899x/585/1/012098
fatcat:scc2pigszrgmtaiqlkiemgevhe
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