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Mapping Statecharts to Verilog for Hardware/Software Co-specification [chapter]

Shengchao Qin, Wei-Ngan Chin
2003 Lecture Notes in Computer Science  
We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.  ...  Hardware-Software co-specification is a critical phase in co-design.  ...  We are also grateful to anonymous referees for many helpful comments.  ... 
doi:10.1007/978-3-540-45236-2_17 fatcat:5pyjzux3kfeapkdyavly6jtcgy

Top Down Approach: SIMULINK Mixed Hardware / Software Design [article]

Youssef Atat, Mostafa Rizk
2012 arXiv   pre-print
System-level design methodologies have been introduced as a solution to handle the design complexity of mixed Hardware / Software systems.  ...  We used the MP3 CodeC application, to validate our approach and methodology.  ...  These lines are modified in a subsystem to define several types of communication topologies between the hardware\software nodes. This topology can be point-topoint, multipoint, network communication.  ... 
arXiv:1207.3872v1 fatcat:uznh3zd6dvboraxxs3cp2td3o4

Using CafeOBJ to Implement a Reduction Strategy in the Context of Hardware/Software Partitioning

André Luis Silva, Manoel Messias Menezes, Leila Silva
2004 Electronical Notes in Theoretical Computer Science  
The focus of this work is hardware/software partitioning verification. The approach uses occam as specification and reasoning language.  ...  In this way, rewriting systems can be regarded as supporting tools for the construction of partitioning environments, whose emphasis is correctness.  ...  Introduction Hardware/Software co-design or simply co-design is a design paradigm for the joint specification, design and synthesis of mixed hardware/software systems.  ... 
doi:10.1016/j.entcs.2004.04.006 fatcat:fgstzyytcvcf5lortkra52n5cq

Using CafeOBJ to Implement a Reduction Strategy in the Context of Hardware/Software Partitioning

A SILVA
2004 Electronical Notes in Theoretical Computer Science  
The focus of this work is hardware/software partitioning verification. The approach uses occam as specification and reasoning language.  ...  In this way, rewriting systems can be regarded as supporting tools for the construction of partitioning environments, whose emphasis is correctness.  ...  Introduction Hardware/Software co-design or simply co-design is a design paradigm for the joint specification, design and synthesis of mixed hardware/software systems.  ... 
doi:10.1016/s1571-0661(04)05015-7 fatcat:lpybs5ektnaxhjkb3f66ruynwi

Design of Embedded Systems: Formal Models, Validation, and Synthesis [chapter]

Stephen Edwards, Luciano Lavagno, Edward A. Lee, Alberto Sangiovanni-Vincentelli
2002 Readings in Hardware/Software Co-Design  
We review the variety of approaches to these problems that have been taken.  ...  Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software.  ...  We also thank Harry Hsieh for his help with a first draft of this work.  ... 
doi:10.1016/b978-155860702-6/50009-0 fatcat:um7k7am5ergnrcizrrkbmzoz7a

SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design

D.D. Gajski, F. Vahid, S. Narayan, Jie Gong
1998 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The new paradigm and environment are expected to lead to a more than ten times reduction in design time, and our experiments support this expectation.  ...  A system-level design option consists of an allocation of system components, such as standard and custom processors, memories, and buses, and a partitioning of functionality among those components.  ...  Hardware/software partitioning techniques form the second functional partitioning category. These techniques focus on partitioning functionality among a hardware/software architecture.  ... 
doi:10.1109/92.661251 fatcat:ctu353p3orgczfzhriawlhzqxq

Hardware/software co-design of global cloud system resolving models

Michael F. Wehner, Leonid Oliker, John Shalf, David Donofrio, Leroy A. Drummond, Ross Heikes, Shoaib Kamil, Celal Kono, Norman Miller, Hiroaki Miura, Marghoob Mohiyuddin, David Randall (+1 others)
2011 Journal of Advances in Modeling Earth Systems  
We demonstrate that hardware/software co-design of low-power embedded processor technology could be exploited to design a custom machine tailored to ultra-high resolution climate model specifications at  ...  paths to realize the integration of such a model in the relatively near future.  ...  As a solution, we propose hardware/software codesign as an approach of using auto-tuned software instead of benchmark codes in the process of hardware design.  ... 
doi:10.1029/2011ms000073 fatcat:dvf567ktnzcorlgzjk66ahwgsm

Inferred Models for Dynamic and Sparse Hardware-Software Spaces

Weidan Wu, Benjamin C. Lee
2012 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture  
In a case study for sparse linear algebra, we present models with 5% median error and new capabilities in coordinated hardware-software tuning.  ...  To address these challenges, we present modeling strategies for integrated hardware-software analysis.  ...  Any opinions, findings, conclusions, or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.  ... 
doi:10.1109/micro.2012.45 dblp:conf/micro/WuL12 fatcat:cqmuqfcuivbutl4qj3kuoqms64

Conformal Computing: Algebraically connecting the hardware/software boundary using a uniform approach to high-performance computation for software and hardware applications [article]

Lenore R. Mullin, James E. Raynolds
2008 arXiv   pre-print
The approach presented in this monograph makes use of A Mathematics of Arrays (MoA, Mullin 1988) and an indexing calculus (i.e. the psi-calculus) to enable the programmer to develop algorithms using high-level  ...  Using a common formalism to describe the problem and the partitioning of data over processors and memory levels allows one to mathematically prove the efficiency and correctness of a given algorithm as  ...  If, in Eq. 3.5, the row length c corresponds to the cache size, the process of combining x(0) and x(4) leads to a cache miss. Likewise combining x(1) and x(5) also leads to a cache miss etc.  ... 
arXiv:0803.2386v1 fatcat:flbqoemiwfh4ljar6jnq3ttpum

Model Checking Memory-Related Properties of Hardware/Software Co-designs [chapter]

Marcel Pockrandt, Paula Herber, Verena Klös, Sabine Glesner
2013 IFIP Advances in Information and Communication Technology  
Hardware/software codesign enables the integrated development of hardware and software in a single design language.  ...  In this thesis, we present an approach for model checking of memoryrelated properties on digital HW/SW systems.  ...  Abstract Hardware/software codesign enables the integrated development of hardware and software in a single design language.  ... 
doi:10.1007/978-3-642-38853-8_9 fatcat:mhkrcphbmvbt7j5kpzecabfi7u

HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform

Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto Sangiovanni-Vincentelli
2002 Proceedings of the tenth international symposium on Hardware/software codesign - CODES '02  
A new mapping flow and algorithms to partition hardware and software are proposed to generate implementation that best utilizes this architecture.  ...  We study a particular architecture platform, which consists of a general purpose processor core, augmented with a reconfigurable function unit and data-path to improve run time performance.  ...  The authors would like to acknowledge Luciano Lavagno for his insightful discussion and comments. We also thank the anonymous reviewers comments and suggestion.  ... 
doi:10.1145/774789.774820 dblp:conf/codes/BaleaniGJPBS02 fatcat:c4hiw5nz5vhtvb6g4zagkrl4ua

Hardware/Software Co-design Flow Using Automatic Generation of Embedded System Framework Based on Interacting FSM Model

Arif Sasongko, School of Electrical Engineering and Informatics Institut Teknologi Bandung Bandung, Indonesia
2020 International Journal on Electrical Engineering and Informatics  
An automatic code generator is developed to produce a framework code from the model.  ...  The generator software takes the model in form of annotated diagrams which are created schematically using a GUI environment. The diagrams follow UML standard.  ...  As the event driven paradigm is used both in the hardware and the software design, hence it is natural to extend this to the hardware/software co-design.  ... 
doi:10.15676/ijeei.2020.12.4.10 fatcat:fzrj25ixbzfahpld7korleauiy

HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform

Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto Sangiovanni-Vincentelli
2002 Proceedings of the tenth international symposium on Hardware/software codesign - CODES '02  
A new mapping flow and algorithms to partition hardware and software are proposed to generate implementation that best utilizes this architecture.  ...  We study a particular architecture platform, which consists of a general purpose processor core, augmented with a reconfigurable function unit and data-path to improve run time performance.  ...  The authors would like to acknowledge Luciano Lavagno for his insightful discussion and comments. We also thank the anonymous reviewers comments and suggestion.  ... 
doi:10.1145/774814.774820 fatcat:o3jj557bxzhingtl3gjngdyyhi

Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design

Nishil Talati, Kyle May, Armand Behroozi, Yichen Yang, Kuba Kaszyk, Christos Vasiladiotis, Tarunesh Verma, Lu Li, Brandon Nguyen, Jiawen Sun, John Magnus Morton, Agreen Ahmadi (+5 others)
2021 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)  
This paper presents Prodigy, a low-cost hardware-software codesign solution for intelligent prefetching to improve the memory latency of several important irregular workloads.  ...  The DIG is then used to program a low-cost hardware prefetcher to fetch data according to an irregular algorithm's data structure traversal pattern.  ...  Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon.  ... 
doi:10.1109/hpca51647.2021.00061 fatcat:noalbamalbdc5gfgetlny3j74y

Worst-case throughput analysis of real-time dynamic streaming applications

Firew Siyoum, Marc Geilen, Orlando Moreira, Henk Corporaal
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
The new technique combines symbolic simulation in Max-plus algebra with worst-case resource curves.  ...  A byproduct of the generalized throughput analysis technique is an approach to verify boundedness of FSM-based SADF models.  ...  The analysis method follows a new approach that combines symbolic simulation in (max, +) algebra with worst-case resource curves (WCRCs).  ... 
doi:10.1145/2380445.2380517 dblp:conf/codes/SiyoumGMC12 fatcat:2vxjwmsjfvaf3dnfsm4k4dmwra
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