852 Hits in 7.2 sec

An Adaptive Feed-Forward Phase Locked Loop for Grid Synchronization of Renewable Energy Systems under Wide Frequency Deviations

Aravind Chellachi Kathiresan, Jeyaraj PandiaRajan, Asokan Sivaprakash, Thanikanti Sudhakar Babu, Md. Rabiul Islam
2020 Sustainability  
Therefore, this paper presents an adaptive feed-forward PLL, where the input signal frequency and phase under large frequency deviations are tracked precisely, which overcomes the above-mentioned limitations  ...  The proposed adaptive PLL consists of a feedback loop that reduces the phase error.  ...  The basic SRF phase-locked loop tracks the input signal phase and frequency using the closed-loop feedback control loop.  ... 
doi:10.3390/su12177048 fatcat:4yahyqes35gb5o6lxel5x5cfpm

Survey on Robust Carrier Tracking Techniques

Jose A. Lopez-Salcedo, Jose A. Del Peral-Rosado, Gonzalo Seco-Granados
2014 IEEE Communications Surveys and Tutorials  
These strategies range from some basic optimizations of current tracking loops, to the use of Kalman filter-based architectures, or the application of innovative carrier tracking techniques based on particle  ...  We will also review some open-loop techniques, which are widely adopted in burstmode communications receivers, as an alternative and potential candidate solution for robust carrier tracking in harsh conditions  ...  Projected loop bandwidth PLL (PLB-PLL) One of the disadvantages of adaptive bandwidth PLL tracking techniques is that they need to permanently estimate some of the input signal parameters, and then use  ... 
doi:10.1109/surv.2013.082713.00228 fatcat:ca6dzkobifd5dcu76rzyo56fiy

An analysis of ADPLL applications in various fields

R. Dinesh, Ramalatha Marimuthu
2020 Indonesian Journal of Electrical Engineering and Computer Science  
In addition, an ADPLL with wide tuning range and frequency resolution is designed and implemented using automatic placement and routing, time to digital converter, digital loop filter and ring based oscillator  ...  ADPLL overcomes the drawbacks of conventional PLL and digital PLL.  ...  A snapshot time-to-digital converter is used to achieve improvement in gain which reduces power consumption. It consists of phase selector, Digital loop filter, LC based DCO and an LMS algorithm.  ... 
doi:10.11591/ijeecs.v18.i2.pp856-866 fatcat:f5syzddqhvchtiercom5f37sb4

Table of Content

2021 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)  
Session D1: Mixed Signal Techniques D1-1 A Compact ThermalSensor with Duty-Cycle Modulation on 1200 um 2 in 7nm FinFET D1-2 An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique  ...  Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips D5-4 An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines Session D6:  ... 
doi:10.1109/vlsi-dat52063.2021.9427313 fatcat:dahcwqnflndbdb4o3hc2g6b7gu

Analysis and design of a frequency-hopped spread-spectrum transceiver for wireless personal communications

J.S. Min, H. Samueli
2000 IEEE Transactions on Vehicular Technology  
Robust acquisition algorithms based on energy detection and pattern matching and tracking architectures using digital phase-locked loops are also described for system synchronization.  ...  High-rate frequency hopping with frequency-shift keying (FSK) modulation is implemented using a direct digital frequency synthesis technique.  ...  A tracking loop requires phase-locked loop (PLL) techniques whose implementation can be completely analog, digital, or a combination of both.  ... 
doi:10.1109/25.892577 fatcat:m7e3k4obvnbrrej3gpiol2hi6e

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

Wanghua Wu, Robert Bogdan Staszewski, John R. Long
2014 IEEE Journal of Solid-State Circuits  
A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed.  ...  A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz  ...  the phase error present in the loop [17] , 2) adaptive gain compensation by a sign-LMS loop [14] , [26] , 3) DCO FB mismatch characterization via an open-loop method [27] , and 4) signal predistortion  ... 
doi:10.1109/jssc.2014.2301764 fatcat:rlafztretzdslovw46qwr263oa

Software Sensors for Order Tracking Applied to Permanent Magnet Synchronous Generator Diagnostics: A Comparative Study

Laurent Rambault, Abdallah Allouche, Erik Etien, Anas Sakout, Thierry Doget, Sebastien Cauet
2021 Robotics  
Four methods are proposed and evaluated to realize software sensors: identification technique, PLL (Phase Locked Loop), Concordia transform and an observer.  ...  The technique targeted is order tracking for which different techniques exist to estimate the speed and angle of rotation.  ...  An alternative is to use a phase in a closed loop structure (Figure 9 ). The system is first order in closed loop.  ... 
doi:10.3390/robotics10020059 fatcat:svrzq26nxfcfjezeqyy2agkpj4

Comparison of Two Three-Phase PLL Systems for More Electric Aircraft Converters

Stefano Bifaretti, Pericle Zanchetta, Elisabetta Lavopa
2014 IEEE transactions on power electronics  
Phase Locked Loop (PLL) based algorithms are commonly used in traditional single and three phase power systems to provide phase and frequency estimations of the supply.  ...  In particular, power electronic converters need accurate control algorithms able to track the fundamental phase and frequency in real time, both in normal and unusual conditions.  ...  For the SSLKF-PLL the closed-loop bandwidth is selected by changing the value of the parameter n; for the DFT-PLL, appropriate values of the proportional and integral gain of the PI loop filter have been  ... 
doi:10.1109/tpel.2014.2307003 fatcat:bays3mijajglndiqqrex7usify

VCO less PLL Control Based VSC for Power Quality improvement in Distributed Generation System

Ashutosh giri, sabha raj arya, Rakesh Maurya, B Chitti Babu
2019 IET electric power applications  
This paper presents the voltage-controlled oscillator (VCO) less phase-locked loop (PLL)-based control of voltage source converter.  ...  Using the proposed control, the reactive power compensation, harmonics reduction and load balancing are carried out in the system.  ...  PLL and SRF-PLL by bode plot, (b) Tracking and balancing act of VCO-less PLL under load dynamics frequency has also appeared.  ... 
doi:10.1049/iet-epa.2018.5827 fatcat:qsq7uspkqfaf5o5rmtyezemobm

Design and Implementation of the Phase-locked Amplifier

Mingxin Song, Fangfang Liu
2015 International Journal of Signal Processing, Image Processing and Pattern Recognition  
It uses the phase sensitive detector (Phase Sensitive Detection, PSD) technique to identify the test signal, which has same frequency with the reference signal, and eliminate the interference noise signal  ...  The signal processing is relatively simple, so it is an effective way to detect the weak signal.  ...  An output signal voltage range is about ± 10V. This frequency and voltage range is capable of meeting most of the weak signal detection.  ... 
doi:10.14257/ijsip.2015.8.5.24 fatcat:2q2glgs7qnhaxergpqfe6hlsqe

Low-Complexity All-Digital Sample Clock Dither for OFDM Timing Recovery

You-Hsien Lin, Terng-Yin Hsu
2010 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
loops.  ...  Based on phase adjustment, this work investigates a low-complexity all-digital sample clock dither (ADSCD) to perform coherent sampling for orthogonal frequency-division multiplexing (OFDM) timing recovery  ...  Unlike other multiphase techniques, e.g., phase-locked loops (PLLs), delay-locked loops (DLLs), and analog circuits, the proposed mechanism is simple yet useful to ensure A/D coherent sampling.  ... 
doi:10.1109/tvlsi.2009.2019079 fatcat:uy7fot2yfrc2jeh3ta6owd2cvu

Evaluation of Quadrature Signal Generation Methods with Reduced Computational Resources for Grid Synchronization of Single-Phase Power Converters through Phase-Locked Loops

Paula Lamo, Alberto Pigazo, Francisco J. Azcondo
2020 Electronics  
Phase-locked loops (PLLs) have been used in this scenario.  ...  and memory units for implementation of the analyzed single-phase PLLs.  ...  Because its frequency response stretches across the entire spectrum, digital realization requires an approximation.  ... 
doi:10.3390/electronics9122026 fatcat:nv6hycb4yjagdorvr6behf63hy

A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR

Heejae Hwang, Jongsun Kim
2020 Electronics  
The proposed CDR uses a new initial phase tracker that uses a preamble to achieve a fast lock time of about 12 ns and to provide a constant output data sequence.  ...  The proposed SerDes receiver with a digital CDR is implemented in 40 nm CMOS technology.  ...  The power detector [37] using the spectrum balancing technique creates a control voltage (VCTRL) that can adaptively adjust the gain of the CTLE.  ... 
doi:10.3390/electronics9071113 fatcat:v3lxf2zpl5hedmgndxlsnyf3um

Radio-Communications Architectures [chapter]

Antoine Diet, Martine Villegas, Genevieve Baudoin, Fabien Robert
2010 Radio Communications  
Each of the Tx and Rx sections deal with unavoidable tradeoffs such as linearity/efficiency (Tx), noise/gain (Rx).  ...  People expect high quality from their different services (QoS) whatever the telecommunications system used.  ...  In this case, an All-Digital Phase Locked Loop (ADPLL) whose input is the phase signal is used.  ... 
doi:10.5772/9469 fatcat:5du2xugg3red3auromiefgt74q

Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial

Bryan Casper, Frank O'Mahony
2009 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Index Terms-Clock distribution, clock recovery, high-speed I/O, phase-locked loops.  ...  It acts as a unity gain buffer for while rejecting supply noise by the loop gain.  ...  Fig. 22 . 22 Conventional analog Type II 2nd order PLL and jitter filtering transfer functions.Fig. 23. Partial control loop for adaptive bandwidth PLL.  ... 
doi:10.1109/tcsi.2008.931647 fatcat:m2zj3kalbvad7ee5m2znin4t7u
« Previous Showing results 1 — 15 out of 852 results