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An 8-bit 150-MHz CMOS A/D converter
2000
IEEE Journal of Solid-State Circuits
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rate of 150 MHz. ...
This paper describes an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers ...
The simple and modular design of the pipelining structure results in a compact layout, requiring a core area of 1.2 mm in a 0.6-µm CMOS process. ...
doi:10.1109/4.826812
fatcat:sqogtfe3tzbjdeblq6x3ssyjnm
An 8-bit 150-MHz CMOS A/D converter
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)
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rate of 150 MHz. ...
This paper describes an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers ...
The simple and modular design of the pipelining structure results in a compact layout, requiring a core area of 1.2 mm in a 0.6-µm CMOS process. ...
doi:10.1109/cicc.1999.777255
fatcat:g6x7ryq3inbefoar2jftqyaf44
Continuous Digital Calibration of Pipeline A/D Converters
2006
IEEE Transactions on Instrumentation and Measurement
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Simulation results show more than 2-bits improvement in the number of effective bits and more than 20 dB improvement in the dynamic range of the converter. ...
The scheme utilizes an existing digital calibration algorithm and extends it to work in real-time. ...
Without using some form of calibration, standard CMOS process technologies limit the resolution of pipeline architecture to approximately 8-10 bits. ...
doi:10.1109/tim.2006.876545
fatcat:un74sdk4nvcl7kljdygk5cytmu
A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling
2003
IEEE Journal of Solid-State Circuits
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Each A/D converter channel operates up to a 640-MHz conversion rate, dissipates 70 mW of power, and occupies an area of 150 m 450 m in a 2.5-V, 0.25-m CMOS technology. ...
An experimental time-interleaved two-channel A/D converter provides about 3.5 effective bits of resolution for inputs up to 40 GHz when tested at an optically-triggered sampling rate of 160 MHz. ...
Harris, Jr. for growth of the LT GaAs and National Semiconductor for fabrication of the CMOS circuits. ...
doi:10.1109/jssc.2003.819172
fatcat:oywhevqxjzgyxnfolbaevwo4jy
150mW, 8ビットビデオ用A/D変換器
A 150-mW, 8-Bit video-Frequency A/D Converter
1985
ITE Technical Report
A 150-mW, 8-Bit video-Frequency A/D Converter
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昭 和 60 年 12 月 20 日 團 発 表 テ レ ビ ジ ョ ン 学 会 技 術 報 告 ED 91． 5 − 50mW ． 8 ビ ッ ト ビ デ オ 用 A ／ D 変 換 ・ 踞 A150 − mW ． 8 − Bit Video − F − ・ equency A ／ D Conver 七 er 堀 田 正 生 ＊ HOTTA Nasao 麻 殖 生 健 二 ・ 清 水 敏 彦 ホ ...
Tsukada ， e し altIJ CMOS 8b 25MHz Flash ADC ， st in ISSCC Dig・ of Tecb ． Papers ， Feb ． 1985， WAM2 ． 7． 2 ］ 」． G． Pe しersen ， レ ， A monolithic video A／D converter ， lt IEEE J ． ...
doi:10.11485/tvtr.9.36_7
fatcat:vctdquud3ngozbzan3voioleni
A 12-b 5-Msample/s two-step CMOS A/D converter
1992
IEEE Journal of Solid-State Circuits
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This paper describes the design of a 12-b, 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a l-pm CMOS technology. ...
The converter dissipates only 200 mW from a single 5-V supply and occupies an area of 2.5 mm x 3.7 mm. 001 8-9200/92$03 .00 @ 1992 IEEE ...
CONCLUSION The design of a 12-b, 5-Msample /s CMOS A/D converter has been described. ...
doi:10.1109/4.173092
fatcat:clzqfijopbhyvbwjmqumb2f3um
Compact FPGA-based beamformer using oversampled 1-bit A/D converters
2005
IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control
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A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. ...
Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz. ...
In this paper, a novel extendable beamformer architecture for use with oversampled 1-bit A/D converters will be presented. ...
doi:10.1109/tuffc.2005.1503973
fatcat:k4o7ttkferawjmdrgeru5dpbgq
A Low-Noise Direct Incremental A/D Converter for FET-Based THz Imaging Detectors
2018
Sensors
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conversion by means of an incremental Σ∆ converter, performing a lock-in operation with modulated sources. ...
The readout chain is fabricated in a standard 150-nm CMOS technology and contains a cascade of a preamplification and noise reduction stage based on a parametric chopper amplifier and a direct analog-to-digital ...
Conclusions In this paper, a noise efficient readout chain integrated with an antenna-coupled FET THz detector has been developed in 150-nm CMOS technology. ...
doi:10.3390/s18061867
pmid:29880744
pmcid:PMC6022096
fatcat:6xi622fomzhtfawsqbryfjq4fu
A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks
2014
JSTS Journal of Semiconductor Technology and Science
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In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. ...
The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB. ...
The SNDR is about 45.35 dB at 150 MHz, and 40 dB at 500 MHz. ...
doi:10.5573/jsts.2014.14.4.376
fatcat:nfwv6g7tsng6pnl3nxnkvdxtly
A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors
2008
IEEE Journal of Solid-State Circuits
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In this paper, a novel 10-bit A/D converter based on a pipeline-like architecture specific for low-noise, self-triggered sensors, (e.g., X-rays and -rays spectrometry) is presented. ...
The main innovative feature of the proposed A/D structure is the concept that, for a sampled input signal, a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal ( ...
The A/D converter in a standard 0.35 m CMOS technology with an active area of 2.24 mm provides a conversion every 2.5 s (400 kS/s) and consumes 14 mW from a 2.3 V power supply. ...
doi:10.1109/jssc.2007.914249
fatcat:zkj6o222ejhcxdcih3ykectdy4
The effect of dielectric relaxation on charge-redistribution A/D converters
1990
IEEE Journal of Solid-State Circuits
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3.3m&s A/D converter. ...
device data from a monolithic capacitor test circuit, describe an empirical capacitor model fit to the rneasnrements, and compare simulated A/D system errors with those observed in a monolithic, 10-b, ...
Fig. 8 . 8 Binary-weighted capacitor array for n-bit A/D converter including dielectric relaxation effects: (a) original network, and (b) transformed network with response current l~~sP defined. ...
doi:10.1109/4.62192
fatcat:5tikxilrezfsbg44bffzbgjo4a
The effect of dielectric relaxation on charge-redistribution A/D converters
1990
Digest of Technical Papers., 1990 Symposium on VLSI Circuits
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3.3m&s A/D converter. ...
device data from a monolithic capacitor test circuit, describe an empirical capacitor model fit to the rneasnrements, and compare simulated A/D system errors with those observed in a monolithic, 10-b, ...
Fig. 8 . 8 Binary-weighted capacitor array for n-bit A/D converter including dielectric relaxation effects: (a) original network, and (b) transformed network with response current l~~sP defined. ...
doi:10.1109/vlsic.1990.111079
fatcat:ev4qlnr4ezajbdv7swqmu3llka
Design of a current mode 6-bit 100 MS/s flash A/D converter with 0.75 pJ/conv-lev FoM
2007
2007 Ph.D Research in Microelectronics and Electronics Conference
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The design of a low-power 6-bit flash A/D converter with state-of-the-art figure of merit for flash architectures is presented. ...
The sampling frequency is 100 MHz and the proposed converter is able to work with an input signal frequency very close to Nyquist rate. ...
Notice that the best reported flash A/D converter with more than 5 bit achieves a FoM of about 2 pJ/conv [3] . ...
doi:10.1109/rme.2007.4401813
fatcat:bmavh6ydxvfhtawapo74awyfhm
A 14b 150 MS/s 140 mW 2.0 mm2 0.13µm CMOS A/D converter for software-defined radio systems
2011
International journal of circuit theory and applications
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This work proposes a 14 b 150 MS/s CMOS A/D converters (ADC) for software-defined radio systems requiring simultaneously high-resolution, low-power, and small chip area at high speed. ...
The ADC with an active die area of 2.0 mm 2 consumes 140 mW at 150 MS/s and 1.2 V. ...
CMOS A/D converter for SDR systems P NA = ∞ 0 S V (f )|A f (j2 f )| 2 df = ∞ 0 64kT 3g m1 1 / 1+(j2 f/ −3dB ) 2 df = 16kT · −3dB 3 2 g m1 (5) Assuming that the maximally allowable noise power for a 14 ...
doi:10.1002/cta.622
fatcat:2vg26r5jqze3bl33dwv437gzsi
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique
2003
Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03
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Simulation results of the proposed fully-differential class-AB op-amp using 0.18um CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than 1mW from a single supply of ...
The proposed op-amp has been designed to be employed in the first stage of a 10bit 150MSamples/sec pipelined analog-to-digital converter. ...
This paper describes a 1-V high speed class-AB operational amplifier which can be used in the first stage of a 1-V 10-bit 150MS/s pipelined A/D converter. ...
doi:10.1145/871589.871591
fatcat:fthhhx4et5einpi5c5qpsecvce
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