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An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Van-Thanh Ta, Van-Phuc Hoang, Van-Phu Pham, Cong-Kha Pham
2020 Electronics  
This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation  ...  The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems.  ...  Conclusions An improved all-digital background calibration technique to calibrate all offset, gain, and timing mismatches for TIADCs was presented.  ... 
doi:10.3390/electronics9010073 fatcat:e2h53xjfkjcdbgdtd3f7vhakjq

A New All-Digital Background Calibration Technique for Time-Interleaved ADC Using First Order Approximation FIR Filters [article]

Jiadong Hu, Zhe Cao, Qi An, Lei Zhao, Shubin Liu
2018 arXiv   pre-print
This paper describes a new all-digital technique for calibration of the mismatches in time-interleaved analog-to-digital converters (TIADCs) to reduce the circuit area.  ...  The proposed technique gives the first order approximation of the gain mismatches and sample-time mismatches, and employs first order approximation FIR filter banks to calibrate the sampled signal, which  ...  channels [7] , and some use Hadamard transform and pseudo aliasing signal [8] [9] [10] .  ... 
arXiv:1806.09120v1 fatcat:rsw73fjifjc75hk5eccpelvfy4

A Background Correlation-Based Timing Skew Estimation Method for Time-Interleaved ADCs

Xin Li, Jianhui Wu, Christian Vogel
2021 IEEE Access  
CONCLUSION In this paper, an all-digital background calibration method for timing skew mismatch in TI-ADCs has been presented.  ...  Correlation-Based Timing Skew Estimation Method for Time-Interleaved ADCs VOLUME XX, 2017 Xin Li et al: A Background Correlation-Based Timing Skew Estimation Method for Time-Interleaved ADCs  ... 
doi:10.1109/access.2021.3067355 fatcat:33urmciwufcv3i6zq72yjbxwn4

A fully digital background calibration of timing skew in undersampling TI-ADC

Han Le Duc, Chadi Jabbour, Patricia Desgreys, Olivier Jamin, Van Tam Nguyen
2014 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)  
This paper proposes a fully digital calibration of timing mismatch for undersampling Time Interleaved Analog-to-Digital Converter (TI-ADC) employed in Software Defined Radio (SDR) receivers.  ...  The efficiency of the proposed technique is shown using a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz.  ...  ACKNOWLEDGMENTS The authors would like to thank the European Catrene AppsGate project for supporting this work.  ... 
doi:10.1109/newcas.2014.6933983 dblp:conf/newcas/DucJDJN14 fatcat:myu46sj7xjezvd3gm7u7k3rvsq

Gain and Offset Mismatch Calibration in Time-Interleaved Multipath A/D Sigma–Delta Modulators

V. Ferragina, A. Fornasari, U. Gatti, P. Malcovati, F. Maloberti
2004 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
In this paper, we propose a digital background adaptive calibration technique for correcting offset and gain mismatches in time-interleaved multipath analog-digital (A/D) sigma-delta (61) modulators.  ...  This solution is also effective for any other time-interleaved A/D converter topology.  ...  . • The input signal is chopped with a pseudo-random sequence consisting of and and the obtained signal is digitized by the th-channel ADC . • The mean value of the digital outputs in one time slot is  ... 
doi:10.1109/tcsi.2004.838154 fatcat:jo4si4qs7ngenawrfaznazepxy

A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Jianwen Li, Xuan Guo, Jian Luan, Danyu Wu, Lei Zhou, Yinkun Huang, Nanxun Wu, Hanbo Jia, Xuqiang Zheng, Jin Wu, Xinyu Liu
2019 Electronics  
This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC).  ...  By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error.  ...  In the background calibration, a pseudo-random signal is sent by the PRBS circuit which is uncorrelated with the input signal. The dither is injected into residue voltage.  ... 
doi:10.3390/electronics8121551 fatcat:bh5krkazkjel7khls5tdkvwdqa

Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges

Yun-Shiang Shu, Stacy Ho, Hsin-Hung Chen, Bala Narasimhan, Kou-Hung Lawrence Loh
2016 APSIPA Transactions on Signal and Information Processing  
The discussion covers design considerations, as well as algorithms used to compensate for circuit imperfections, so as to demonstrate the cross-discipline interactions between signal processing and analog  ...  The increasing demand for high-data rate communications in the connected world imposes various challenges in analog and radio frequency (RF) circuits.  ...  Zhan, Guang-Kaai Dehng, Chih-Ming Hung, and Zoran Zvonar for their helpful advices and technical discussions.  ... 
doi:10.1017/atsip.2016.12 fatcat:gyzi25y7wzajvp4qazgbae423a

A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection

Chung-Yi Wang, Jieh-Tsorng Wu
2009 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
The proposed calibration scheme does not demand stringent requirement for the reference input. Its application to a eight-channel 6-b time-interleaved analog-to-digital converter is demonstrated.  ...  It has better immunity against the offsets of the comparators used in the detector. A digital calibration processor is also proposed.  ...  There are calibration schemes for TI ADCs that directly use the input of the ADC as the reference for timing-skew detection [2], [9] . Those schemes inherently operate in the background.  ... 
doi:10.1109/tcsi.2008.2008477 fatcat:euxfk7cebvgfjdp64rdpejlb7e

A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC

Inseok Jung, Kyung Ki Kim, Yong-Bin Kim
2015 Journal of Integrated Circuits and Systems  
This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor  ...  The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.  ...  For example, 1 LSB is 244.14 μV in the 12bit SAR ADC using 1V V ref . The impact of the offset errors is much more detrimental in time-interleaved ADCs [23] .  ... 
doi:10.29292/jics.v10i3.422 fatcat:bpxbi2vlwzgnvoyl6n7vvlhamq

A Pitch-Matched Front-End ASIC With Integrated Subarray Beamforming ADC for Miniature 3-D Ultrasound Probes

Chao Chen, Zhao Chen, Deep Bera, Emile Noothout, Zu-Yao Chang, Mingliang Tan, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs
2018 IEEE Journal of Solid-State Circuits  
To achieve power-efficient massively parallel analog-to-digital conversion (ADC) in a 2-D array, a 10-bit 30 MS/s beamforming ADC that merges the subarray beamforming and digitization functions in the  ...  Index Terms-3-D ultrasound imaging, charge-sharing successive approximation register (SAR) analog-to-digital conversion (ADC), in-probe digitization, miniature probes, subarray beamforming, ultrasound  ...  By doing so, the beamformer and the digitizer are essentially merged together: the delay lines perform as a multichannel time-interleaved input sampler in a charge-sharing SAR ADC [32] .  ... 
doi:10.1109/jssc.2018.2864295 fatcat:z3gzm2y4dfbfrdxbqdl6wv4p5y

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski
2021 IEEE Journal of Solid-State Circuits  
Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital  ...  This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC).  ...  Teerachot Siriburanon for help with the tapeout; the Microelectronic Circuits Centre Ireland (MCCI) for technical and administrative support; Suoping Hu and Hieu Minh Nguyen for technical discussions;  ... 
doi:10.1109/jssc.2021.3114006 fatcat:p3f2esux3va35foamn2yexq52u

2020 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 67

2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., +, TCSI Aug. 2020 2588-2601 An Efficient Spur-Aliasing-Free Spectral Calibration Technique in Time-In- terleaved ADCs.  ...  Tu, J., +, TCSI Nov. 2020 4015-4028 An Efficient Spur-Aliasing-Free Spectral Calibration Technique in Time-In- terleaved ADCs.  ...  ., +, 3297-3308 Self-Tuned Class-D Audio Amplifier With Post-Filter Digital Feedback Implemented on Digital Signal Controller.  ... 
doi:10.1109/tcsi.2021.3055003 fatcat:kbmst5td2bbvtl7vpbj3knnkri

All-passive pixel super-resolution of time-stretch imaging

Antony C. S. Chan, Ho-Cheung Ng, Sharat C. V. Bogaraju, Hayden K. H. So, Edmund Y. Lam, Kevin K. Tsia
2017 Scientific Reports  
It harnesses the subpixel shifts between image frames inherently introduced by asynchronous digital sampling of the continuous time-stretch imaging process.  ...  Here, we propose a pixel super-resolution (pixel-SR) technique tailored for time-stretch imaging that preserves pixel resolution at a relaxed sampling rate.  ...  This work is conducted in part using the HKU ITS research computing facilities that are supported in part by the Hong Kong  ... 
doi:10.1038/srep44608 pmid:28303936 pmcid:PMC5356014 fatcat:542i4gwfzvhvzgwdrvgbxe76sm

Accurate and robust spectral testing with relaxed instrumentation requirements

Yuming Zhuang, Degang Chen
2017 2017 IEEE International Test Conference (ITC)  
For the best performance of the DAC, the DAC’s maximum output frequency is more than 10 times the generated sine wave. Thus, the sine wave is viewed as pseudo static.  ...  Since the spectral analysis is done in the digital domain, the output signals after circuits and systems are often digitized by Analog-to-Digital Converters (ADCs).  ... 
doi:10.1109/test.2017.8242081 dblp:conf/itc/ZhuangC17 fatcat:vehzcinrgngbrkbwh4xipkisqe

Wireless, Ultra-Low-Power Implantable Sensor for Chronic Bladder Pressure Monitoring

Steve J. A. Majerus, Steven L. Garverick, Michael A. Suster, Paul C. Fletter, Margot S. Damaser
2012 ACM Journal on Emerging Technologies in Computing Systems  
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage  ...  using less power.  ...  As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.  ... 
doi:10.1145/2180878.2180883 pmid:26778926 pmcid:PMC4712728 fatcat:3zhcflfxqrgexcis7dm7sxqzwa
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