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All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash
2021
IEEE Access
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INDEX TERMS All-bit-line (ABL) sensing, BL pre-charge, BL locking, multi-level cell, NAND flash, page buffer, sense node amplification. ...
A NAND flash memory senses a cell current in the range of tens of nA, which is smaller than other nonvolatile memories in the read operation. ...
To read the data in a NAND flash cell quickly, NAND flash adopts the all-bit-line (ABL) sensing architecture instead of The associate editor coordinating the review of this manuscript and approving it ...
doi:10.1109/access.2021.3058391
fatcat:fvaszlnb4fgobdlazwghzizxki
2019 Index IEEE Solid-State Circuits Letters Vol. 2
2019
IEEE Solid-State Circuits Letters
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., +, LSSC July 2019 53-56 Flash memories A 24-MB Embedded Flash System Based on 28-nm SG-MONOS Featuring 240-MHz Read Operations and Robust Over-the-Air Software Update for Automotive Applications. ...
., +, LSSC Sept. 2019 119-122
An All-Digital, V MAX -Compliant, and Stable Distributed Charge Injection
Scheme for Fast Mitigation of Voltage Droop. ...
doi:10.1109/lssc.2020.2967202
fatcat:ka56gc64uvfvbjddesloe5qmnu
In‐Memory Vector‐Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor‐Memristor Integrated Circuits: Design Choices, Challenges, and Perspectives
2020
Advanced Intelligent Systems
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In this context, resistive switching (RS) memory devices is a key promising choice, due to their unique intrinsic device-level properties enabling both storing and computing with a small, massively-parallel ...
In-memory computing has emerged as a prime candidate to eliminate this bottleneck by co-locating the memory and processing. ...
ML-CSA is minimizing the offset in sense amplifier due to the mismatch of CMOS devices in the bit-line. ...
doi:10.1002/aisy.202000115
fatcat:jbumwsdpwze33paahq5qul2cja
Technologies for Ultradynamic Voltage Scaling
2010
Proceedings of the IEEE
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Trend in minimum energy point of a 32 b adder with process scaling using predictive models [31]. ...
Second, we describe a 0.3 V 16-bit microcontroller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc-dc converter. Fig. 5. ...
Acknowledgment The authors would like to acknowledge Dimitri Antoniadis, Yu Cao, Eric Wang, and Wei Zhao for help with predictive technology models. ...
doi:10.1109/jproc.2009.2033621
fatcat:ehsup4tsbfa67ccdre7wvt26yq
A New Test Paradigm for Semiconductor Memories in the Nano-Era
2011
2011 Asian Test Symposium
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This is in contrary to voltage mode sense amplifiers where the data once stored in output register is locked, and is not affected even when there is a change in voltage levels of bit line. ...
The read circuity consists of a sense amplifier, which can sense the state of the bit line(s) after a read operation. ...
doi:10.1109/ats.2011.87
dblp:conf/ats/HamdiouiKIA11
fatcat:qibwo2zc6zeghhnihyrea47ntu
1 GS/s, low power flash analog to digital converter in 90nm CMOS technology
2012
2012 International Conference on Multimedia Computing and Systems
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After last stage the amplified remainder will feed into 4 Bit flash ADC that will generate 4 least significant bits. ...
2-Bit ADC 76
Figure 6 . 6 11: Bubble Correction Block for 2-Bit ADC 77
Figure 6 . 6 12: 3 Input AND with 2 Inverted Bits 3 Input NAND gate and inverter was designed by complementary CMOS logic and ...
The coding of file writer for 2 bits is as follows:
SNR Estimation The output will store in outputfile.dat as matrix. We will then read this file in Matlab to estimate SNR. ...
doi:10.1109/icmcs.2012.6320209
dblp:conf/icmcs2/ChakirQ12
fatcat:s6d7ot5uqjdfxhxoutdgh5lorq
2019 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 66
2019
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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Li,
C., +, TCSI June 2019 2322-2335
Flash memories
A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications. ...
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS. ...
Analysis of SRAM Enhancements Through Sense Amplifier ...
doi:10.1109/tcsi.2020.2966967
fatcat:f663jj5g45e3peggn3gwn5jys4
2018 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 65
2018
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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., and Pandey, N ...
., +, TCSI Dec. 2018 4183-4195 Flash memories Decision-Directed Retention-Failure Recovery With Channel Update for MLC NAND Flash Memory. ...
., +, TCSI May 2018 1591-1601 Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs. ...
doi:10.1109/tcsi.2019.2896877
fatcat:3lzpngw2ofdjhiculf7ehrjeam
A dual-core 64-bit ultraSPARC microprocessor for dense server applications
2005
IEEE Journal of Solid-State Circuits
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The 206-mm 2 die is fabricated in 0.13-m CMOS technology with seven layers of Cu and a low-k dielectric. ...
A dual-core 64-bit microprocessor optimized for compute-dense systems such as rack-mount and blade servers for network computing was developed. ...
The data is protected with 64 ECC bits for each line (8-bits per 64-bit datum) to support single-bit correction and double-bit detection. ...
doi:10.1109/jssc.2004.838023
fatcat:pdfny6iuzzc57ic6xcq3u6dlt4
2021 Index IEEE Journal of Solid-State Circuits Vol. 56
2021
IEEE Journal of Solid-State Circuits
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This index covers all technical items-papers, correspondence, reviews, etc.-that appeared in this periodical during 2021, and items from previous years that were commented upon or corrected in 2021. ...
The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. ...
., +, JSSC Jan. 2021 43-54 An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Com-plementary Dynamic Amplifiers in 28-nm CMOS. ...
doi:10.1109/jssc.2021.3137574
fatcat:nfo3y7i5kncsng36fvi5g5hdre
2020 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 67
2020
IEEE Transactions on Circuits and Systems - II - Express Briefs
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Agrawal, A., and Roy, K., Functional Read Enabling In-Memory Computations in 1Transistor-1Resistor Memory Arrays; TCSII Dec. 2020 3347-3351 Jalali, M., see Kabirpour, S., TCSII Feb. 2020 250-254 Jalali ...
Discrete-Time Singular Systems With Actuator Saturation and Uncertainties; 340-344 Jagabar Sathik, M., Sandeep, N., Almakhles, D., and Blaabjerg, F., Cross Connected Compact Switched-Capacitor Multilevel ...
., +, TCSII April 2020 625-629
Dynamic Read Current Sensing With Amplified Bit-Line Voltage for STT-
MRAMs. ...
doi:10.1109/tcsii.2020.3047305
fatcat:ifjzekeyczfrbp5b7wrzandm7e
Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things
2017
Electronics
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logic locking, and a TFET secure SAR ADC design for Trojan countermeasures are shown in Section 6. ...
all-spin logic devices are highlighted. ...
Jin Lin contributes to low power SAR ADC and hybrid ΔƩ SAR ADC designs. Qutaiba Alasa makes a contribution in polymorphic gate logic locking using silicon nanowire and all spin logic devices. ...
doi:10.3390/electronics6030067
fatcat:ozssarlb2ng5pcdsupo2hljyna
Trends on the application of emerging nonvolatile memory to processors and programmable devices
2013
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
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., "Trends on the application of emerging nonvolatile memory to processors and programmable devices," Circuits and Sys-Torres, L.; Brum, R.M.; Guillemenet, Y.; Sassatelli, G.; Cargnini, L.V., "Evaluation ...
M.; Guillemenet, Y.; Sassatelli, G., "Embedded MRAM for high-speed computing," VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/I- ...
sense amplifiers. ...
doi:10.1109/iscas.2013.6571792
dblp:conf/iscas/TorresBCS13
fatcat:aommoaizybhufp76nxuappbxby
2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26
2018
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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., and Chang, S., Contactless Testing for Prebond Interposers; TVLSI June 2018 1005-1014 Hsu, Y., see Liu, Z., 1565-1574 Hu, J., see Wang, Y., TVLSI May 2018 805-817 Hu, J., see Li, Y., 1585-1589 ...
., +, TVLSI Jan. 2018 110-121
A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive
Nonvolatile Memories. ...
., +, TVLSI April 2018 756-767
Flash memories
A Progressive Performance Boosting Strategy for 3-D Charge-Trap NAND
Flash. ...
doi:10.1109/tvlsi.2019.2892312
fatcat:rxiz5duc6jhdzjo4ybcxdajtbq
Understanding and Improving the Latency of DRAM-Based Memory Systems
[article]
2017
arXiv
pre-print
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In stark contrast with capacity and bandwidth, DRAM latency has remained almost constant, reducing by only 1.3x in the same time frame. ...
The key conclusion of this dissertation is that augmenting DRAM architecture with simple and low-cost features, and developing a better understanding of manufactured DRAM chips together lead to significant ...
Hence, the sense amplifier is able to sense and latch bit 1 faster than 0. ...
arXiv:1712.08304v1
fatcat:6y2nr2eowvb5fhr7km7azmkioe
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