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Investigation Into Prs Precoded, Constant-envelope, Continuous Phase Digital Modulation Schemes

J.N. Golby, R.M. Braun
IEEE South African Symposium on Communications and Signal Processing  
National Semiconductor, Data Conversion/Acquisition Data Book, 1984. National Semiconductor, Linear Data Book, 1984 Saal, R., Handbook of filter Design, 1979, AEG-Telefunken.  ...  Carrier recovery is straightforward -:---" a peak-to-peak jitter of about 4% is achieved with fairly simple circuitry.  ...  Two DAC0800 D/A converters convert the sine and cosine digital words into an oversampled analog signal.  ... 
doi:10.1109/comsig.1990.658534 fatcat:yx7nmwrrrbf7rn6d4zdls6urbe

Radio interferometry techniques for geodesy

1979 Bulletin Géodésique  
All the observatories, with two or three exceptions, have the Mark II recording system based on Ampex or IVC recorders, and two observatories are experimenting with video cassette recorder.  ...  Correlation and further processing of the data is carried out, for the most part, using the threestation Mark II processor at the Max Planck Institut fiir Radioastronomie in Bonn, Germany.  ...  Along with the digital data, clock signals which are synchronous with the data are sent to the digital tone extractor.  ... 
doi:10.1007/bf02521643 fatcat:2wf6omvyrfeb7iq56xseifrpxe

Energy-Detecting Receivers for Wake-Up Radio Applications

Vivek Mangal
2019
A fully integrated wake-up receiver uses the self-mixer and time-encoded baseband signal processing to provide a sensitivity of -79.1dBm at 434MHz with 420pW of power, providing an 8dB better sensitivity  ...  The architecture uses pulse-position-encoded analog signal processing with VCOs as integrators and pulse-controlled relaxation delays; it operates as a code-domain matched filter to de-spread asynchronous  ...  The Digital Correlator The receiver does not do data-clock recovery but uses 2x oversampling to receive the wake-up code [23, 24] .  ... 
doi:10.7916/d8-mf65-r747 fatcat:4akntdcmgvdlvercnbdgwuyf7i

Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Appllications [article]

Robert Bogdan Staszewski
2002 unpublished
The binary input data is being oversampled by a commonly-used 13 MHz frequency reference (FREF) clock generated by a crystal oscillator, which is an integer multiple of the 1 Mbps data (or symbol) Figure  ...  Resampling Pulse filter h(t) Binary data sequence Resampled data sequence Filter output Oversampling clock (FREF) Table 5 . 5 1.  ... 
doi:10.13140/rg.2.1.1975.4326 fatcat:3rrnnvkihnh3hmuv7u4aurjrnm

The Multi-Sampling Digital Tanlock Loop for tracking suppressed-carrier M-ary PSK signals

Joël A. Bisson
1989
Unlike the conventional Digital Phase-Locked Loop (DPLL) which possesses a sinusoidal phase characteristic, the MDTL has a linear phase characteristic with a period of 2π/M.  ...  It is shown that the use of multi-sampling improves the performance of the MDTL over the conventional Digital Tanlock Loop by increasing the region of stability and consequently, the lock range, and by  ...  When a block is sent, the time required to obtain lock with an acquisition probability of 0.9 may be used.  ... 
doi:10.14288/1.0064770 fatcat:telgtgd6yrgebgtoln4zbl4h5i

HARMONIC RF SENSING: FROM INDOOR LOCALIZATION TO VITAL-SIGN MONITORING

Xiaonan Hui
2021
Meanwhile because all tags in CDMA respond simultaneously, the sampling clock jitter is minimized.  ...  The resolutions of 50 μm in air and 5 μm in water with 1 kHz refresh rate were presented by the 1 GHz RF sensing system.  ...  Alternatively, we can use the phased array to generate "phase map" from a single reading location and measure the angel of arrival to retrieve the spherical coordinates with just ranging.  ... 
doi:10.7298/r3gk-9b84 fatcat:uxmva6koznhn3jtoyraagavova

Transceiver architectures and sub-mW fast frequency-hopping synthesizers for ultra-low power WSNs [article]

Lopelli, E (Emanuele), Roermund, AHM (Arthur) Van, Tang, JD (Johan) Van Der
2010
After the incoming signal has been downconverted to baseband a high sampling rate digitizer is used to convert the incoming data into the digital domain.  ...  Furthermore, the requirement on the clock generation circuitry can be very demanding in terms of jitter.  ...  In this case equation (A.2) can be written as follows: while equation (A.5) becomes: Finally, the 3 rd order harmonic rejection, in the presence phase error between the signals applied to the interpolator  ... 
doi:10.6100/ir657018 fatcat:jgkmw2djxfevlpiv2x7at7fwim

Carrier recovery for coherent optical communication systems

JIGNESH DHRUVAKUMAR JOKHAKAR
2018
Considering these different requirements, this thesis explores different approaches to carrier recovery namely: digital signal processing, optoelectronic processing and all-optical processing.  ...  Carrier recovery and synchronization are the base foundation for data extraction in any coherent communication system.  ...  Until 2017, the highest transmission reach achieved without errors is 300 km using FSK for 300 Mbps and the highest data rate achieved was 10 Gbps using FSK for 40 km transmission link.  ... 
doi:10.26180/5b4789a9836d8 fatcat:vlf66rqzizfozakhcljt6lhujq

Error Behaviour In Optical Networks

Laura Bryony James, Apollo-University Of Cambridge Repository, Apollo-University Of Cambridge Repository, Ian White
2017
Empirical data is used to enhance this original analysis, making it directly relevant to deployed systems.  ...  Some data payloads suffer from high bit error rates and low packet loss rates, compared to others with lower bit error rates and yet higher packet losses.  ...  Possible candidates for a clock recovery solution would be PLLs, an oversampling scheme, or some other more advanced digital coding technique.  ... 
doi:10.17863/cam.11801 fatcat:qp6m7nz6ivgqlnnkw5ix2s2fmi