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A two-dimensional topological compactor with octagonal geometry
1991
Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91
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W e present a two-dimensional layout compactor with octagonal geometry. W e discuss layout optimization algorithms used within a topological framework. ...
This version of the compactor uses an iterative greedy layout optimization algorithm with wire minimization and produces leafcells more compact than others published. ...
T h e algorithms provide full two-dimensional compaction using octagonal geometry and automatically make optimal wire jogs. ...
doi:10.1145/127601.127759
dblp:conf/dac/DoodWLS91
fatcat:dvxyesv5ljcy5pccjezb4ro3xa
A new layout synthesis for leaf cell design
1995
Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC '95
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We propose a new layout synthesis with 2-dimensional transistor arrangement and a spontaneous process of 2-dimensional compaction and local re-routing. ...
The compaction enables jumping over objects, minimizing the number of contacts for wiring. We applied the layout synthesis to actual cell design and obtained comparable results to handcrafted design. ...
Kuninobu of Semiconductor Research Center for their supporting and encouraging our research. ...
doi:10.1145/224818.224907
dblp:conf/aspdac/FukuiSA95
fatcat:cebvpbsqbbfihjfb2efnzuqadu
A hierarchy preserving hierarchical compactor
1990
Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90
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This paper describes a one-dimensional compactor which simultaneously compacts the contents of all cells of a layout hierarchy without changing the hierarchy. ...
Using dedicated Simplex algorithms for compaction and wire length minimization, a globally optimum result is produced quickly and efficiently without the use of protection frames or domains and terminals ...
Acknowledgements The author is grateful to Henk Hegen for writing the code for generating compaction constraints and to both Henk and John Conway for running compaction benchmarks and providing valuable ...
doi:10.1145/123186.123311
dblp:conf/dac/Marple90
fatcat:nyokb354g5d6nhbhcalo3urbuy
Page 4541 of Mathematical Reviews Vol. , Issue 91H
[page]
1991
Mathematical Reviews
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Finally, the section on compaction describes one- and two-dimensional compaction and hierarchical compaction. ...
Summary: “The complexity of adding two n-bit numbers on a two- dimensional systolic array is investigated. ...
Layout optimization by pattern modification
1990
Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90
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This paper introduces a new and practical approach to several layout optimization problems. ...
A novel two-dimensional pattem generator, in connection with a set of routing and placement transformations, is employed to efficiently solve problems ranging from Wire Crossing Minimization and Topological ...
Non-optimal MSTs (that is, MSTs with extra twistings and comers) may be observed in the layout [6] . We set two criteria for deciding between two Steiner trees. ...
doi:10.1145/123186.123424
dblp:conf/dac/Hojati90
fatcat:jw5w4fg5ibainmnbfdzqb73k5i
The future of custom cell generation in physical synthesis
1997
Proceedings of the 34th annual conference on Design automation conference - DAC '97
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In particular, we describe three opportunities for coupling circuit optimization operations with the library development process. ...
These operations include electrical optimization, technology mapping, and cell level place and route. ...
Compaction Compaction is the process of generating compact and error free layout from an initial symbolic or generic layout. ...
doi:10.1145/266021.266196
dblp:conf/dac/LefebvreMS97
fatcat:yr4tbi6pu5gxrdjche4b27xxla
CELLERITY
1997
Proceedings of the 34th annual conference on Design automation conference - DAC '97
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This paper describes a fully automatic standard-cell layout synthesis system, CELLERITY. ...
The tool is fully automatic and provides several options to the user to customize the layout template. The tool considers performance and yield and generates dense, design-rule correct layouts. ...
Second, the router maps the symbolic layout problem onto a non-uniform two-dimensional virtual routing grid whose objective is to maximize the number of routing tracks that can be used in all the routing ...
doi:10.1145/266021.266126
dblp:conf/dac/GuruswamyMDRCFJ97
fatcat:xh46v2repjfafpxrisrffc4j4m
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts
2006
Computer-Aided Design (ICCAD), IEEE International Conference on
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Using a two-dimensional hybrid scheme of graph-based optimization and nonlinear programming, the nonlinear problem is solved effectively and efficiently. ...
In this paper, we present a novel algorithm that performs parasitic-aware automatic layout retargeting for analog/RF integrated circuits. ...
This paper proposes a template-based two-dimensional nonlinear optimization algorithm for parasitic-aware layout retargeting. ...
doi:10.1145/1233501.1233570
dblp:conf/iccad/JangkrajarngZBKS06
fatcat:xf5dahmkordxvnhe6rle3twp2i
Template-Based Parasitic-Aware Optimization and Retargeting of Analog and RF Integrated Circuit Layouts
2006
Computer-Aided Design (ICCAD), IEEE International Conference on
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Using a two-dimensional hybrid scheme of graph-based optimization and nonlinear programming, the nonlinear problem is solved effectively and efficiently. ...
In this paper, we present a novel algorithm that performs parasitic-aware automatic layout retargeting for analog/RF integrated circuits. ...
This paper proposes a template-based two-dimensional nonlinear optimization algorithm for parasitic-aware layout retargeting. ...
doi:10.1109/iccad.2006.320056
fatcat:zdazrlmjtrgs7e665sqwan2vfy
Layout-oblivious compiler optimization for matrix computations
2013
ACM Transactions on Architecture and Code Optimization (TACO)
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Therefore separately optimizing the operations and the data layout of a computation could dramatically enhance the effectiveness of compiler optimizations compared with the conventional approaches of using ...
We evaluated our approach on an Intel 8-core platform using two source-to-source compiler infrastructures, Pluto and EPOD. ...
The algorithm is shown in Algorithm 2 and takes two parameters, the input code to analyze, and a symbol table which stores the existing result of analysis. ...
doi:10.1145/2400682.2400694
fatcat:24fhy46qvbgc7g3webltf4b5hi
Review of power module automatic layout optimization methods in electric vehicle applications
2020
Chinese Journal of Electrical Engineering
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By reviewing element representation, placement, routing, fitness evaluation, and the optimization algorithm approaches, a state-of-the-art power module layout design method for electric vehicle applications ...
For electrical layout, optimizing the parasitic parameters can improving switching loss and dynamic behavior. ...
In the layout design of a power module, the three-dimensional (3D) physical variables are usually simplified and mapped onto a two-dimensional (2D) model to reduce complexity. ...
doi:10.23919/cjee.2020.000015
fatcat:5tyftf4lwfho7du2nqeuladixy
An Improved Flower Pollination Algorithm for Optimizing Layouts of Nodes in Wireless Sensor Network
2019
IEEE Access
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This paper presents an improved flower pollination algorithm based on a hybrid of the parallel and compact techniques for global optimizations and a layout of nodes in WSN. ...
INDEX TERMS Improved flower pollination algorithm, layout optimization problems, probabilistic model, wireless sensor network. ...
We then optimize the mathematical model of the problem in WSN. Table 5 shows an example of representation the location of sensor nodes in two-dimensional coordinates. ...
doi:10.1109/access.2019.2921721
fatcat:ymoclpob2jgndkx765u3q4axvm
Layout compaction with attractive and repulsive constraints
1990
Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90
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A one-dimensional compaction algorithm with attractive and repulsive constraints is proposed. ...
In the following, we describe the compaction algorithm with repulsive constraints first, the compaction algorithm with attractive constraint next, and finally with both constraints, for the sake of convenience ...
Miyashita for their helpful discussions and continuous encouragement. ...
doi:10.1145/123186.123308
dblp:conf/dac/Onozawa90
fatcat:ujqvkiljh5b3ngpwuumnfdrrhi
D&T Conferences
1987
IEEE Design & Test of Computers
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For the first time, ICCAD 86 formed two subcommittees for international participation: one for Asia and one for Europe. ...
The conference hotel, the Doubletree, opened only two weeks before the conference. ...
Krakow, MCNC The International Workshop on Symbolic Layout and Compaction debuted with an open and frank discussion of compaction algorithms and the role of symbolic layout in chip development. ...
doi:10.1109/mdt.1987.295117
fatcat:rrfgfupilbbwbnuhq4igsd4tzu
Correct-by-construction layout-centric retargeting of large analog designs
2004
Proceedings of the 41st annual conference on Design automation - DAC '04
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Aggressive design cycles in the semiconductor industry demand a design-reuse principle for analog circuits. ...
This paper presents a computer-aided design tool and the methodology for a layoutcentric reuse of large analog intellectual-property blocks. ...
of a new layout from the template is based on symbolic compaction [10] . ...
doi:10.1145/996566.996609
dblp:conf/dac/BhattacharyaJHS04
fatcat:pjqtd334y5f2jh7z3j6tws7rha
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