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Algorithms and Lower Bounds for Comparator Circuits from Shrinkage

Bruno P. Cavalar, Zhenjian Lu, Mark Braverman
2022
In this paper, we initiate the study of average-case complexity and circuit analysis algorithms for comparator circuits.  ...  This average-case lower bound matches the worst-case lower bound of Gál and Robere by letting k = O(log n). - #SAT Algorithms.  ...  Oliveira for numerous helpful discussions and comments.  ... 
doi:10.4230/lipics.itcs.2022.34 fatcat:iwg34tuemnagnlmfcehjpoomo4

Satisfiability Algorithms for Restricted Circuit Classes [article]

Stefan Schneider
2013 arXiv   pre-print
A special focus is given to connections between satisfiability algorithms and circuit lower bounds.  ...  This survey takes a (far from exhaustive) look at some recent satisfiability algorithms for a range of circuit classes and high- lights common themes.  ...  Acknowledgment: I thank Ramamohan Paturi for helpful comments on an earlier draft. References [1] A.E. Andreev. On a method for obtaining more than quadratic effictive lower bounds for π-schemes.  ... 
arXiv:1306.4029v1 fatcat:qgbopbcdbvhcvaatfili7fyele

Page 6860 of Mathematical Reviews Vol. , Issue 2001I [page]

2001 Mathematical Reviews  
Buffer-overflow and cell-loss probabilities are defined. The last sec- tion contains asymptotic upper and lower bounds to over-flow and loss probabilities.  ...  lower error than our procedure.” 20011:94007 94A08 Chrétien, Stephane (B-ULB-GS; Brussels) ; Hero, Alfred O., II] (1-MI-EE; Ann Arbor, MI) Kullback proximal algorithms for maximum-likelihood estimation  ... 

Fourier Concentration from Shrinkage

Russell Impagliazzo, Valentine Kabanets
2016 Computational Complexity  
, and Γ = 1/ log 2 ( √ 5−1) ≈ 3.27 for read-once de Morgan formulas.  ...  For a Boolean function f : {0, 1} n → {1, −1} computable by a de Morgan formula of size s, we show that where Γ is the shrinkage exponent for the corresponding class of formulas: Γ = 2 for de Morgan formulas  ...  We also thank Ilan Komargodski and Avishay Tal for their comments on an early version of the paper; special thanks to Avishay for pointing out an error (in the proof of Theorem IV.1) in an early version  ... 
doi:10.1007/s00037-016-0134-y fatcat:czv5akwlnnaubcnhalr2s6nxqq

Fourier Concentration from Shrinkage

Russell Impagliazzo, Valentine Kabanets
2014 2014 IEEE 29th Conference on Computational Complexity (CCC)  
, and Γ = 1/ log 2 ( √ 5−1) ≈ 3.27 for read-once de Morgan formulas.  ...  For a Boolean function f : {0, 1} n → {1, −1} computable by a de Morgan formula of size s, we show that where Γ is the shrinkage exponent for the corresponding class of formulas: Γ = 2 for de Morgan formulas  ...  We also thank Ilan Komargodski and Avishay Tal for their comments on an early version of the paper; special thanks to Avishay for pointing out an error (in the proof of Theorem IV.1) in an early version  ... 
doi:10.1109/ccc.2014.39 dblp:conf/coco/ImpagliazzoK14 fatcat:xrlhsaa2x5b2nbn6udykgvzn2a

Pseudorandomness from Shrinkage

Russell Impagliazzo, Raghu Meka, David Zuckerman
2012 2012 IEEE 53rd Annual Symposium on Foundations of Computer Science  
lower bounds but do know lower bounds of a fixed polynomial.  ...  One powerful theme in complexity theory and pseudorandomness in the past few decades has been the use lower bounds to give pseudorandom generators (PRGs).  ...  Acknowledgments We are grateful to Avi Wigderson for useful discussions and suggestions.  ... 
doi:10.1109/focs.2012.78 dblp:conf/focs/ImpagliazzoMZ12 fatcat:qnmowrrq2vbq7h3g2gnemdfrxa

The exact complexity of pseudorandom functions and the black-box natural proof barrier for bootstrapping results in computational complexity

Zhiyuan Fan, Jiatu Li, Tianqi Yang
2022 Symposium on the Theory of Computing  
We also present an 𝑛 1+Ω (𝑐 −𝑑 ) wire complexity lower bound against depth-𝑑 TC 0 circuits for some 𝑐 > 1.61.  ...  We resolve the exact complexity of PRFs by proving tight upper and lower bounds for various circuit models. • PRFs can be constructed in 2𝑛 + 𝑜 (𝑛) size general circuits assuming the existence of polynomial-size  ...  We thank Lijie Chen, Hanlin Ren, and Ryan Williams for the insightful discussion; and Lijie Chen for proofreading an earlier draft of the paper.  ... 
doi:10.1145/3519935.3520010 dblp:conf/stoc/FanL022 fatcat:axkbbap6tbf3bd7456k7lgsahq

The Exact Complexity of Pseudorandom Functions and Tight Barriers to Lower Bound Proofs [article]

Zhiyuan Fan, Jiatu Li, Tianqi Yang
2021 IACR Cryptology ePrint Archive  
Perhaps surprisingly, we prove extremely tight upper and lower bounds in various circuit models. • In general B 2 circuits, assuming the existence of PRFs, PRFs can be constructed in 2n + o(n) size, simplifying  ...  and improving the O(n) bound by Ishai et al.  ...  Acknowledgement We are greatly thankful to Yilei Chen for his support throughout this project and providing lots of useful comments. We also thank Lijie Chen and Ryan Williams for useful discussion.  ... 
dblp:journals/iacr/FanL021 fatcat:6k5d5ucoizh3bjbydxhlpwqvw4

Page 2410 of Mathematical Reviews Vol. , Issue 96d [page]

1996 Mathematical Reviews  
Lower and upper bounds for the min- imal depth of function-computing trees are established.  ...  We also show how cover theory lends insight to the performance of hillclimbing algorithms and genetic algorithms, and present data from simulations that support a covers-based explanation for genetic algorithm  ... 

Automatic transistor and physical design of FPGA tiles from an architectural specification

Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
We describe a new placement tool that simultaneously places and compacts the layout to minimize white space and wiring demand, and a specialpurpose router built for this task.  ...  In this paper we present a new system (called GILES, for Good Instant Layout of Erasable Semiconductors) that automatically generates a transistor-level schematic from a high-level architectural specification  ...  We chose to compare to the Xilinx Virtex-E device (built in 0.18µm CMOS process from UMC) and the Altera Apex 20K400E device (built in a 0.18µm CMOS process from TSMC).  ... 
doi:10.1145/611839.611842 fatcat:tfou5dycafcdhasuepukrcqjqi

Automatic transistor and physical design of FPGA tiles from an architectural specification

Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
We describe a new placement tool that simultaneously places and compacts the layout to minimize white space and wiring demand, and a specialpurpose router built for this task.  ...  In this paper we present a new system (called GILES, for Good Instant Layout of Erasable Semiconductors) that automatically generates a transistor-level schematic from a high-level architectural specification  ...  We chose to compare to the Xilinx Virtex-E device (built in 0.18µm CMOS process from UMC) and the Altera Apex 20K400E device (built in a 0.18µm CMOS process from TSMC).  ... 
doi:10.1145/611817.611842 dblp:conf/fpga/PadaliaFBER03 fatcat:ddh7ykb75bbkhjhm7fxmnoh2tu

How to Find Water in the Ocean: A Survey on Quantified Derandomization [article]

Roei Tell
2021 Electronic colloquium on computational complexity  
How small does this probability need to be in order for the problem's complexity to be affected?  ...  The focus of this survey is the question of quantied derandomization, which was introduced by Goldreich and Wigderson (2014): Does derandomization of probabilistic algorithms become easier if we only want  ...  And I'm grateful to William Hoza for sharing his proof of Theorem D.1 and for his permission to include it in the survey.  ... 
dblp:journals/eccc/Tell21 fatcat:dntqqo67ercrzjkog66xz4iyxu

A New Normalized Subband Adaptive Filter Algorithm with Individual Variable Step Sizes

Yi Yu, Haiquan Zhao, Badong Chen
2015 Circuits, systems, and signal processing  
Furthermore, a noniterative shrinkage method is used to recover the noise-free a priori subband error from the noisy subband error signal.  ...  lower steady-state error.  ...  The proposed algorithm assigns an individual step size for each subband and uses the noniterative shrinkage method reported in [17] to estimate the noise-free a priori subband error signals.  ... 
doi:10.1007/s00034-015-0112-7 fatcat:v7d6zce4ybg2lpjejudg5uqole

Integration of RFID Network Planning with Xbee Network: A New Approach

Khalid Hasnan, Aftab Ahmed, Badrul Aisham, Qadir Bakhsh, Kamran Latif, Kashif Hussain
2016 International Journal of Smart Home  
RFID system is able to reduce the product loss or shrinkage and bullwhip effect resulting to reduce the overall cost.  ...  AI has two major branches such as Evolutionary Algorithm (EA) and Swarm Intelligence (SI) and its further developed techniques are as shown in Figure 1 [ [11] [12] [13] .  ...  [Xmin , Xmax], where Xmin is the lower bound and Xmax is the upper bound of the readers position.  ... 
doi:10.14257/ijsh.2016.10.4.28 fatcat:bgjdw42ckvhgnkyjcpnz7fmxvi

Hardness Magnification near State-Of-The-Art Lower Bounds

Igor Carboni Oliveira, Ján Pich, Rahul Santhanam, Michael Wagner
2019 Computational Complexity Conference  
For instance, the lower bound assumed in (1) holds for U2-formulas of near-quadratic size, and lower bounds similar to (3)-( 5 ) hold for various regimes of parameters.  ...  These results are complemented by lower bounds for Gap-MCSP and Gap-MKtP against different models.  ...  Gap-MCSP and lower bounds for NP.  ... 
doi:10.4230/lipics.ccc.2019.27 dblp:conf/coco/OliveiraPS19 fatcat:ktnzcfls3jfijcl373bmxv7tva
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