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Algorithmic implementation of low-power high performance FIR filtering IP cores

C.H. Wang, A.T. Erdogan, T. Arslan
18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design  
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores.  ...  On the other hand, multiple data paths are utilized for achieving high performance. The paper presents the complete architectural implementation of these algorithms for high performance applications.  ...  This paper presents the implementation of high throughput and low power FIR filtering Intellectual Property (IP) cores.  ... 
doi:10.1109/icvd.2005.44 dblp:conf/vlsid/WangEA05 fatcat:ssuahu7hwzhu3f2hcdnhv5bovy

Automated Design Space Exploration for DSP Applications

Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser Alexander
2008 Journal of Signal Processing Systems  
Our framework synthesizes designs from a high level of abstraction into well-constructed and recognizable hardware structures that perform well in terms of area, throughput and power dissipation.  ...  We utilize our framework to estimate hardware performance using a set of pre-synthesized mathematical cores which expedites the synthesis process by approximately 14 fold.  ...  ACKNOWLEDGMENTS The work of Ramsey Hourani was supported by the Office of Naval Research and Historically Black Engineering Colleges (ONR/HBEC) Future Engineering Faculty Fellowship Program.  ... 
doi:10.1007/s11265-008-0226-2 fatcat:angbfbzirjf5fha24fcolofgzq

Quantization of VLSI digital signal processing systems

Gabriel Caffarena, Olivier Sentieys, Daniel Menard, Juan A. López, David Novo
2012 EURASIP Journal on Advances in Signal Processing  
implementation and precision analysis of key IP cores for multimedia and communication systems and, (iii) the precision-wise high-level synthesis of DSP algorithms.  ...  However, certain applications require the use of dedicated hardware to achieve high computation rates and low power.  ...  Acknowledgements The guest editors would like to thank the work of both authors and reviewers.  ... 
doi:10.1186/1687-6180-2012-32 fatcat:jrw2oy3ronc2rgyghqqzkja25q

Software Implementation Of Shdsl Transceivers On A Novel Dsp Architecture

Manfred Riener, Andreas Bolzer, Gerald Krottendorfer
2004 Zenodo  
Publication in the conference proceedings of EUSIPCO, Viena, Austria, 2004  ...  Since the processing power of available low-power DSP cores does not provide the required execution speed, high performing xDSL transceivers are implemented as dedicated hardware (HW) solutions.  ...  Current general purpose DSPs promise high processing power, but only few signal processors are available as IP core [2, 3] .  ... 
doi:10.5281/zenodo.38406 fatcat:54kwsqriofbg5c7bvgrpogqhke

Design and Realization of FIR Digital Filter for Optical IM/DD-OFDM System Using FPGA

HAO-ZE LI, HUI-BIN ZHANG, JIE ZHANG, YONG-LI ZHAO, KAI WANG, YONG SUN
2018 DEStech Transactions on Computer Science and Engineering  
The implementation results showed decent performance in filtering.  ...  We present a finite impulse response (FIR) filter by using field programmable gate array (FPGA). It is designed in MATLAB, and we get filter coefficient from it.  ...  Xilinx zynq7020 FPGA has rich resource to complete the design, in addition, Xilinx corporation provides intellectual property core (IP core) resource, which includes high performance FIR filter IP core-FIR  ... 
doi:10.12783/dtcse/cimns2017/17454 fatcat:clkqc2ievjdbzjvioldvrn4lpy

Low Power System-on-Chip Platform Architecture for High Performance Applications [chapter]

W.-C. Lo, A. T. Erdogan, T. Arslan
2003 The Kluwer International Series in Engineering and Computer Science  
Initial results are provided with a low power FIR filter core demonstrating impact of power on various sections of the platform.  ...  This paper describes work on the development of a scheme for implementation of low power high performance Digital Signal Processing intensive AMBA based System-On-Chip platforms.  ...  CONCLUSION The authors have presented a low power platform for the implementation of high performance DSP intensive tasks.  ... 
doi:10.1007/978-1-4615-0351-4_32 fatcat:4v5qfbbsundi5hcke7qmvxzjg4

FPGA Implementation of Variable Digital Filter using MicroBlaze Processor

M. Rupa, CVR College of Engineering, Department of ECE, Ibrahimpatan, R.R.District, A.P., India, Karthik Kumar Rayabandi, CVR College of Engineering, Department of ECE, Ibrahimpatan, R.R.District, A.P., India
2012 CVR Journal of Science & Technology  
This VDF is best suited for realization of digital filter algorithms, which are low-pass, high-pass, band-pass and band-stop filter algorithms with variable frequency domain characteristics.  ...  Unlike conventional digital filter, Variable Digital Filters (VDFs) can change their filter-type, number of taps and coefficients constantly such that the desired frequencydomain characteristics can be  ...  low-pass, high-pass, band-pass, and band-stop.  ... 
doi:10.32377/cvrjst0307 fatcat:oeing4ex6nclvcztsfcpt7y6m4

POWER EFFICIENT AND HIGH THROUGHPUT OF FIR FILTER USING BLOCK LEAST MEAN SQUARE ALGORITHM IN FPGA

M.Devipriya .
2014 International Journal of Research in Engineering and Technology  
In silicon on chip technology demands high performance and low power Very Large Scale Integrated Circuit (VLSI) digital signal processing (DSP) systems.  ...  An adaptive FIR filter with Block Least Mean Square (BLMS) algorithm was developed to reduce the power.  ...  One way to efficiently incorporate high performance design technique is to implement IP cores.  ... 
doi:10.15623/ijret.2014.0314001 fatcat:seac5jz2xfcuxgb62574qivzby

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Jean Shilpa V, P.K. Jawahar
2021 International Journal of Systems Control and Communications  
It employs cores with varying capabilities to achieve high performance computation. This paper proposes a hybrid structure of CPU and FPGA (HCF) heterogeneous, hard and soft-core custom processor.  ...  Algorithms have been proposed for efficient utilisation of the proposed hybrid processor to work as a platform of work for the software demanding high speed and performance metrics.  ...  Abdur Rahman Crescent Institute of science and technology for giving an opportunity to evaluate the system using Xilinx Vivado simulator and Zedboard.  ... 
doi:10.1504/ijscc.2021.10035685 fatcat:w3eovue6lndqhnrxman4o7az3q

Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller

Mangi Han, Youngmin Kim
2019 Electronics  
When power level is too low or too high, the repeater is required to compensate the power level and ensure a stable signal.  ...  The proposed system exploits various digital signal-processing algorithms, which include modulation, demodulation, Cascaded Integrator Comb (CIC) filters, Finite Impulse Response (FIR) filters, Interpolated  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/electronics8050482 fatcat:rd3jho63ifbxnfbepoothf47pq

DESIGN OF FIR FILTER ALGORITHM FOR NOISE REMOVAL IN ECG SIGNAL USING OPEN CORE SoC

2021 International Journal of Advanced Trends in Computer Science and Engineering  
Among the many DSP applications, the FIR filter has been implemented on an open core SoC platform that uses RISCV. Here specifically filtering of noise from ECG signal.  ...  This has provided the path to implement various functions on an open core SoC Platform.  ...  Acknowledgment The authors gratefully acknowledge the facilities and support provided by the director of the school of Electronics And Communication Engineering of REVA UNIVERSITY, We also extend thanks  ... 
doi:10.30534/ijatcse/2021/791022021 fatcat:vrslmr6asnaqho2tuihr3fhnbm

AN FPGA IMPLEMENTATION OF THE LMS ADAPTIVE FILTER FOR ACTIVE VIBRATION CONTROL

Shashikala Prakash .
2013 International Journal of Research in Engineering and Technology  
The floating point LMS algorithm in VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language), uses the Intellectual Property (IP) cores available from Xilinx Inc.  ...  This paper brings out implementation of Least Mean Square (LMS) algorithm using two different architectures.  ...  These resources are implemented on the FPGA fabric and optimized for high performance and low power consumption.  ... 
doi:10.15623/ijret.2013.0210001 fatcat:erkdjmihyjfnvlffnsmd7o6rza

Separable FIR Filtering in FPGA and GPU Implementations: Energy, Performance, and Accuracy Considerations

Daniel Llamocca, Cesar Carranza, Marios Pattichis
2011 2011 21st International Conference on Field Programmable Logic and Applications  
In this paper, we present a dynamically reconfigurable implementation of a 2D FIR filter where the number of coefficients and coefficients values can be varied to control energy, performance, and precision  ...  Results using a standard example of 2D Difference of Gaussians (DOG) filter indicate that the DPR implementation can deliver real-time performance with energy per frame consumption that is an order of  ...  Moreover, these 2 implementations allow the user to modify the 2D FIR Filter at run-time.  ... 
doi:10.1109/fpl.2011.71 dblp:conf/fpl/LlamoccaCP11 fatcat:uwa6wwzx3naipmztlrsqiuuxba

Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language

Lekhobola Tsoeunyane, Simon Winberg, Michael Inggs
2017 International Journal of Reconfigurable Computing  
This paper reports on the design and implementation of an open-source library of parameterizable and reusable Hardware Description Language (HDL) Intellectual Property (IP) cores designed for the development  ...  The operation of the SDR cores is first validated and then benchmarked against two other cores libraries of a similar type to show that our cores do not take much more logic elements than existing cores  ...  Conflicts of Interest The authors declare that there are no conflicts of interest regarding the publication of this paper.  ... 
doi:10.1155/2017/3925961 fatcat:5hj7giryl5ex7kfpu37zcuomti

An optimal architecture for a DDC

T. Bijlsma, P.T. Wolkotte, G.J.M. Smit
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
A possible DDC algorithm consists of two simple Cascading Integrating Comb (CIC) filters and a Finite Input Response (FIR) filter preceded by a modulator that is controlled with a Numeric Controlled Oscillator  ...  All architectures are functionally capable of performing the algorithm. The differences between the architectures are their performance, flexibility and energy consumption.  ...  Acknowledgement This research is conducted within the Smart Chips for Smart Surroundings project (IST-001908) supported by the Sixth Framework Programme of the European Community.  ... 
doi:10.1109/ipdps.2006.1639440 dblp:conf/ipps/BijlsmaWS06 fatcat:qw6fgdqepbfvfmhgr5ymrximc4
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