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Efficient Synthesis Of Consistent Graphs

Martin Kreißig
2010 Zenodo  
Publication in the conference proceedings of EUSIPCO, Aalborg, Denmark, 2010  ...  SYNTHESIS ALGORITHMS In this section, we present systematic approaches for the efficient synthesis of consistent graphs given sets of weights W i (1 ≤ i ≤ N).  ...  This algorithm is called Kirchhoff Potential Synthesis with Pruning (KiPoS-P).  ... 
doi:10.5281/zenodo.42063 fatcat:xcpugq4cvrf7zl5a4qx5mexyq4

Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction

Ian G. Harris, Alex Orailoglu
1997 VLSI design (Print)  
Such libraries allow the generation of an accurate estimate of the area and delay of the final design during synthesis.  ...  Accurate design descriptions during synthesis allow efficient use of resources. The appropriate use of distinct implementations of RTL operators helps generate optimal VLSI designs.  ...  A preliminary version of this paper has been presented in ISCAS9319].  ... 
doi:10.1155/1997/81902 fatcat:oznewaa2mbeozou452zjkntdhm

Pattern-based behavior synthesis for FPGA resource reduction

Jason Cong, Wei Jiang
2008 Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays - FPGA '08  
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations.  ...  The edit distance between two graphs is the minimum number of vertex/edge insertion, deletion, substitution operations to transform one graph into the other.  ...  (c) Binary branches and CV of the given DAG modified for pattern pruning.  ... 
doi:10.1145/1344671.1344688 dblp:conf/fpga/CongJ08 fatcat:36wq4o2e2zgqznyaop6bcvejky

Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions

Andrew Seawright, Wolfgang Meyer
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
to control the synthesis process.  ...  The methods utilize the structure of the high-level description, provide flexible exploration of the trade-off between combinational logic and registers to reduce implementation cost, and allow the designer  ...  The state graph generation algorithm will assume that the shift register can fill with any binary value without using the sequential behavior of the start signal to prune the graph.  ... 
doi:10.1145/277044.277239 dblp:conf/dac/SeawrightM98 fatcat:f2zg4dbxrrbtjio57vqorkjiku

Synthesis Algorithm for Application-Specific Homogeneous Processor Networks

J. Cong, K. Gururaj, Guoling Han, Wei Jiang
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Specifically, the result of our algorithm is latency-optimal for directed acyclic task graphs.  ...  We employ a novel framework for this problem, similar to that of technology mapping in the logic synthesis domain, and develop a set of efficient algorithms, including labeling and clustering for efficient  ...  ACKNOWLEDGMENT The authors would like to thank Dr. I. Bolsen from Xilinx, Inc., for his stimulating discussion on synthesis of networks of soft-core processors.  ... 
doi:10.1109/tvlsi.2008.2004874 fatcat:ujsw4vlcwvbahnuqggrq3xzw3e

Iterative Bounded Synthesis for Efficient Cycle Detection in Parametric Timed Automata [chapter]

Étienne André, Jaime Arias, Laure Petrucci, Jaco van de Pol
2021 Lecture Notes in Computer Science  
The algorithms traverse a possibly infinite parametric zone graph, searching for accepting cycles. We provide new search and pruning algorithms, leading to successful termination for many examples.  ...  We demonstrate the success and efficiency of these algorithms on a benchmark. We also illustrate parameter synthesis for the classical Bounded Retransmission Protocol.  ...  Our contributions to the parameter constraint synthesis for liveness of PTA are: 1) A definition of soundness and completeness for non-terminating algorithms. 2) A new synthesis algorithm, using bounded  ... 
doi:10.1007/978-3-030-72016-2_17 fatcat:jol2k7vgwfhtfmu62ziorx77p4

Pattern-Mining for Behavioral Synthesis

Jason Cong, Hui Huang, Wei Jiang
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Our algorithm uses a feature-based filtering approach for fast pruning, and a graph similarity metric called the generalized edit distance for measuring variations in control-data flow graphs.  ...  Our approach is very scalable in benefit of advanced pruning techniques. The similarity of structures is captured by a mismatchtolerant metric: the graph edit distance.  ...  Next, patterns are viewed as complex multicycle operations, and any state-of-the-art behavior synthesis algorithm can be easily adapted for PBS-RR problem. V.  ... 
doi:10.1109/tcad.2011.2106370 fatcat:tgwcqg67yzdclosrsfe7nbvefu

Research on Road Finding Under Complicated Constraints Based on Ant Colony Algorithm

Ke WANG, Yi-fan PENG, Xiu-qi ZHANG, Dr Yougar
2018 DEStech Transactions on Computer Science and Engineering  
First, build a network pruning, and use the Dijkstra algorithm to generate a secondary synthesis network diagram, and then make use of ant colony algorithm in the secondary synthesis network diagram to  ...  This method is competent to satisfy the cost priority of path-finding under constraint and complex conditions.  ...  of ant colony algorithm in the secondary synthesis network diagram to search for paths.  ... 
doi:10.12783/dtcse/cmee2017/19981 fatcat:axzgbfquyjhmpa2xbt66bdgm6i

Accelerating FPGA design space exploration using circuit similarity-based placement

Xiaoyu Shi, Dahua Zeng, Yu Hu, Guohui Lin, Osmar R. Zaiane
2010 2010 International Conference on Field-Programmable Technology  
This paper describes a novel and fast placement algorithm for field programmable gate array (FPGA) design space exploration.  ...  Tested on logic-level and algorithm-level design space exploration cases, our similarity-based placement accurately depicts the "shape" of a design space and pinpoints the designs which are of most interest  ...  For our algorithm, we use an iterative graph similarity algorithm for molecular graphs [11] , which takes advantage of the graph sparsity, one of the properties of a circuit graph.  ... 
doi:10.1109/fpt.2010.5681424 dblp:conf/fpt/ShiZHLZ10 fatcat:nqxehd2ecfdfdmgvvyemsiwrpu

Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures

Subhendu Roy, Mihir Choudhury, Ruchir Puri, David Z. Pan
2013 Proceedings of the 50th Annual Design Automation Conference on - DAC '13  
For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of prefix graph subject to constraints like bit-wise  ...  This paper proposes an efficient algorithm to synthesize prefix graph structures that yield adders with the best performancearea trade-off.  ...  Let smin be the size of the minimum sized prefix graph(s) of Gn. Then we prune the solutions (g) for which size(g) > smin +∆.  ... 
doi:10.1145/2463209.2488793 dblp:conf/dac/RoyCPP13 fatcat:higjaeja3zgj3mvr3momxqvfna

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures

Subhendu Roy, Mihir Choudhury, Ruchir Puri, David Z. Pan
2014 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of prefix graph subject to constraints like bit-wise  ...  This paper proposes an efficient algorithm to synthesize prefix graph structures that yield adders with the best performancearea trade-off.  ...  Let smin be the size of the minimum sized prefix graph(s) of Gn. Then we prune the solutions (g) for which size(g) > smin +∆.  ... 
doi:10.1109/tcad.2014.2341926 fatcat:uofhx6e5dff5lht7cu5gllftsy

PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning [article]

Rajarshi Roy, Jonathan Raiman, Neel Kant, Ilyas Elkin, Robert Kirby, Michael Siu, Stuart Oberman, Saad Godil, Bryan Catanzaro
2022 arXiv   pre-print
Unlike prior methods, our approach designs solutions tabula rasa purely through learning with synthesis in the loop.  ...  Deep Convolutional RL agents trained on this environment produce prefix adder circuits that Pareto-dominate existing baselines with up to 16.0% and 30.2% lower area for the same delay in the 32b and 64b  ...  Algorithm 1: PrefixRL N-input prefix graph actions B. Scalarized Double Deep Q Learning PrefixRL uses a scalarized version of the Double-DQN algorithm [23] .  ... 
arXiv:2205.07000v1 fatcat:r2eg2qrzonglta6a5kmkwobady

Enhancement of incremental design for FPGAs using circuit similarity

Xiaoyu Shi, Dahua Zeng, Yu Hu, Guohui Lin, Osmar R. Zaiane
2011 2011 12th International Symposium on Quality Electronic Design  
As a case study, we perform the proposed IDUCS process to generate the placement for a logically resynthesized netlist based on the placement of the original netlist and the circuit similarity between  ...  Furthermore, IDUCS simply inserts a plugin for circuit similarity detection, and therefore preserves the "push-button" feature, significantly simplifying the engineering complexity of incremental tasks  ...  In this work, we use an iterative graph similarity algorithm for molecular graphs [14] , which takes advantage of graph sparsity, one of the properties of a circuit graph.  ... 
doi:10.1109/isqed.2011.5770732 dblp:conf/isqed/ShiZHLZ11 fatcat:7sd5zmjypfbwdcht34dthwuduy

Data communication estimation and reduction for reconfigurable systems

Adam Kaplan, Philip Brisk, Ryan Kastner
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Our algorithm reduces the data communication (measured as total edge weight in a control data flow graph) by as much as 20% for some applications as compared to the best-known SSA algorithm -the pruned  ...  However, the placement of Φ-nodes by current SSA algorithms is not optimal in terms of minimizing data communication.  ...  For example, the TEW for the benchmark fft2 using the semi-pruned algorithm is approximately 5 times that of the pruned algorithm.  ... 
doi:10.1145/775983.775987 fatcat:r7j7mikfjbcgbocx4wyd54nfte

Data communication estimation and reduction for reconfigurable systems

Adam Kaplan, Philip Brisk, Ryan Kastner
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Our algorithm reduces the data communication (measured as total edge weight in a control data flow graph) by as much as 20% for some applications as compared to the best-known SSA algorithm -the pruned  ...  However, the placement of Φ-nodes by current SSA algorithms is not optimal in terms of minimizing data communication.  ...  For example, the TEW for the benchmark fft2 using the semi-pruned algorithm is approximately 5 times that of the pruned algorithm.  ... 
doi:10.1145/775832.775987 dblp:conf/dac/KaplanBK03 fatcat:mbau255vhbfijobhofkhtxtieu
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