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Architectural considerations for application-specific counterflow pipelines

B.R. Childers, J.W. Davidson
1999 Proceedings 20th Anniversary Conference on Advanced Research in VLSI  
Sutherland, Sproull, and Molnar have proposed a new pipeline organization called the Counterflow Pipeline (CFP).  ...  Fourth, we show that asynchronous counterflow pipelines achieve high-performance by reducing the average execution latency of instructions over synchronous implementations.  ...  Because the arbiter controls the advancement of results and instructions in the pipeline, it should be made as fast as possible.  ... 
doi:10.1109/arvlsi.1999.756034 dblp:conf/arvlsi/ChildersD99 fatcat:sm2hu2vhrvghjeifj2ca3p7zem

Custom wide counterflow pipelines for high-performance embedded applications

B.R. Childers, J.W. Davidson
2004 IEEE transactions on computers  
Using an analytic cost model, we show that custom WCFPs do not unduly increase the cost of the original counterflow pipeline architecture, yet they retain the simplicity of the CFP.  ...  Sutherland, Sproull, and Molnar originally proposed a processor organization called the counterflow pipeline (CFP) as a general-purpose architecture.  ...  ACKNOWLEDGMENTS The authors would like to thank the reviewers for their careful reading and helpful comments on the initial manuscript.  ... 
doi:10.1109/tc.2004.1261825 fatcat:pswfmrtejjglxcwtnfoanf4m7q

Coming challenges in microarchitecture and architecture

R. Ronen, A. Mendelson, K. Lai, Shih-Lien Lu, F. Pollack, J.P. Shen
2001 Proceedings of the IEEE  
In the past several decades, the world of computers and especially that of microprocessors has witnessed phenomenal advances.  ...  In this paper, we describe the role of microarchitecture in the computer world, present the challenges ahead of us, and highlight areas where microarchitecture can help address these challenges.  ...  One such approach is the counterflow microarchitecture [62] , in which results are pipelined and flow in an opposing direction as instructions. 3) Soft Error Rate: Soft errors are inevitable with technology  ... 
doi:10.1109/5.915377 fatcat:iywintmu5jeltngkqn6h3ryh7u

Razor: circuit-level correction of timing errors for low-power operation

D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin, T. Mudge, Nam Sung Kim, K. Flautner
2004 IEEE Micro  
This is evident in the evolution of mobile phones: in the past seven years, mobile phones have shown a 50× improvement in talk-time per gram of battery (based on a comparison of standard configurations  ...  For instance, local process variations will affect specific regions of the die in different and  ...  Acknowledgments We extend thanks to the numerous additional contributors to the Razor project, including Toan Pham, Sanjay Pant, Rajeev Rao, Conrad Ziesler, Dave Roberts, and Valeria Bertacco.  ... 
doi:10.1109/mm.2004.85 fatcat:2nezhnjuwvhypp6u2snl7jz6dq

Making typical silicon matter with Razor

T. Austin, D. Blaauw, T. Mudge, K. Flautner
2004 Computer  
Razor, 1 a voltage-scaling technology based on dynamic detection and correction of circuit timing errors, permits design optimizations that tune the energy in a microprocessor pipeline to typical circuit  ...  A n old adage says, "If you're not failing some of the time, you're not trying hard enough."  ...  Acknowledgments This work was supported by ARM, an Intel Graduate Fellowship, the Defense Advanced Research Projects Agency, the Semiconductor Research Corporation, the Gigascale Silicon Research Center  ... 
doi:10.1109/mc.2004.1274005 fatcat:f6ogrfauyrdo5adqz2quqigvpy

Performance Analysis of Timing-Speculative Processors

Omid Assare, Rajesh Gupta
2021 IEEE transactions on computers  
the financial support that made this dissertation possible. I am grateful for the freedom I had to explore and change direction and the opportunity to learn and practice independent thinking.  ...  Error signals of all Figure 2 . 2 7a and 2.7b show the microarchitecture design of counterflow pipelining and a timing diagram of the pipeline during the recovery of a timing error in the EX stage.  ...  Counterflow pipelining, therefore, incurs a recovery penalty of 2N cycles where N is the maximum (in case of multiple errors) depth of the errant stages in the pipeline.  ... 
doi:10.1109/tc.2021.3051877 fatcat:nkkie5fnx5hybmnjaf52qux36y

Identifying and predicting timing-critical instructions to boost timing speculation

Jing Xin, Russ Joseph
2011 Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11  
To a large extent existing work has relied on statistical error models and has not evaluated potential disparity of error rates at the level of static instructions.  ...  We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and error padding techniques to avoid the full recovery cost of timing errors.  ...  Second, counterflow pipeline recovery used in Razor-like designs is sensitive to the pipeline depth of timing errors.  ... 
doi:10.1145/2155620.2155636 dblp:conf/micro/XinJ11 fatcat:hn5pdtpbybbqbo3b3ta7tgaoji

An infrastructure for designing custom embedded counterflow pipelines

B.R. Childers, J.W. Davidson
Proceedings of the 33rd Annual Hawaii International Conference on System Sciences  
We have developed a new microarchitecture for automatically constructing ASIPs. This new architecture, called a wide counterflow pipeline (WCFP), is based on the counterflow pipeline (CFP).  ...  Application-specific instruction set processor (ASIP) design is a promising approach for meeting the performance and cost goals of an embedded system.  ...  Wide Counterflow Pipelines The WCFP is a VLIW microarchitecture that issues several operations per instruction to exploit ILP in kernel loops.  ... 
doi:10.1109/hicss.2000.926966 dblp:conf/hicss/ChildersD00 fatcat:ts7kvkmdvbeqflqpgicth6duuu

Custom wide counterflow pipelines for high performance embedded applications

B.R. Childers, J.W. Davidson
Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)  
Using an analytic cost model, we show that custom WCFPs do not unduly increase the cost of the original counterflow pipeline architecture, yet they retain the simplicity of the CFP.  ...  Sutherland, Sproull, and Molnar originally proposed a processor organization called the counterflow pipeline (CFP) as a general-purpose architecture.  ...  ACKNOWLEDGMENTS The authors would like to thank the reviewers for their careful reading and helpful comments on the initial manuscript.  ... 
doi:10.1109/pact.2000.888331 dblp:conf/IEEEpact/ChildersD00 fatcat:jclrvg6yqfcr5mebobsudswa5y

Cyclone

Dan Ernst, Andrew Hamel, Todd Austin
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
Our approach utilizes a listbased single-pass instruction scheduling algorithm, implemented by hardware at run-time in the front end of the processor pipeline.  ...  In this paper, we present the Cyclone scheduler, a novel design that captures the benefits of both compileand run-time scheduling.  ...  Acknowledgements We would like to thank all of our reviewers and collegues for their insights and suggestions for strengthening our paper.  ... 
doi:10.1145/859618.859647 fatcat:7pnwk7urxrephgzefourahvi4q

Cyclone

Dan Ernst, Andrew Hamel, Todd Austin
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
Our approach utilizes a listbased single-pass instruction scheduling algorithm, implemented by hardware at run-time in the front end of the processor pipeline.  ...  In this paper, we present the Cyclone scheduler, a novel design that captures the benefits of both compileand run-time scheduling.  ...  Acknowledgements We would like to thank all of our reviewers and collegues for their insights and suggestions for strengthening our paper.  ... 
doi:10.1145/859644.859647 fatcat:27mzonv3b5f5hpcpw5ym2jzvou

Cyclone

Dan Ernst, Andrew Hamel, Todd Austin
2003 SIGARCH Computer Architecture News  
Our approach utilizes a listbased single-pass instruction scheduling algorithm, implemented by hardware at run-time in the front end of the processor pipeline.  ...  In this paper, we present the Cyclone scheduler, a novel design that captures the benefits of both compileand run-time scheduling.  ...  Acknowledgements We would like to thank all of our reviewers and collegues for their insights and suggestions for strengthening our paper.  ... 
doi:10.1145/871656.859647 fatcat:j5kmtbgdcrgmhp24bc4fnh3tva

Elastic Circuits

J. Carmona, J. Cortadella, M. Kishinevsky, A. Taubin
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous design.  ...  Thus, choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.  ...  Active antitokens implement a counterflow of information in the elastic circuits and therefore are reminiscent of the counterflow pipeline from [107] .  ... 
doi:10.1109/tcad.2009.2030436 fatcat:6anbrdoea5hjhf3gsjp3myxvuq

Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software

Abbas Rahimi, Luca Benini, Rajesh K. Gupta
2016 Proceedings of the IEEE  
We provide a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software.  ...  We conclude with an outlook for the emerging field.  ...  Similarly, in counterflow pipelining when an error is occurred within a stage, the stage sends a bubble toward end of pipeline stages and a flush toward head of pipeline stages (the fetch stage).  ... 
doi:10.1109/jproc.2016.2518864 fatcat:sxrsu3excbdg5p7sk4iczz262y

Dynamically reducing overestimated design margin of MultiCores

Toshinori Sato, Takanori Hayashida, Ken Yano
2012 2012 International Conference on High Performance Computing & Simulation (HPCS)  
MultiCore processor is one of the promising techniques to satisfy computing demands of the future consumer devices.  ...  the assumption of typical delay.  ...  The authors would like to thank Shunitsu Kohara of Toshiba Corporation for helping them use MeP simulator.  ... 
doi:10.1109/hpcsim.2012.6266944 dblp:conf/ieeehpcs/SatoHY12 fatcat:6fehue5wrnaznnd3pdg6aqhtai
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