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Verification of configurable processor cores

Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas
2000 Proceedings of the 37th conference on Design automation - DAC '00  
This paper presents a verification methodology for configurable processor cores.  ...  A configurable and extensible test-bench serves as the framework for the verification process and offers components necessary for the complete SOC verification.  ...  The authors are especially grateful to the entire hardware team for building this verification methodology and for their insightful comments on drafts of the paper.  ... 
doi:10.1145/337292.337527 dblp:conf/dac/Puig-MedinaEK00 fatcat:kpkv4qfykvcg7ncpi3upk6el6m

Smart diagnostics for configurable processor verification

Sadik Ezer, Scott Johnson
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica's latest configurable processor.  ...  Conventional simulation-based verification methodologies that employ assembly programs for testing cannot easily link the diagnostic program to the test-bench for interactive control, consequently resulting  ...  CONFIGURABLE VERIFICATION INFRASTRUCTURE Developing a test-bench for functional verification of a configurable processor is challenging in many ways.  ... 
doi:10.1145/1065579.1065789 dblp:conf/dac/EzerJ05 fatcat:pijgw5r6b5fllh3mqozyzvbtpq

Smart diagnostics for configurable processor verification

S. Ezer, S. Johnson
2005 Proceedings. 42nd Design Automation Conference, 2005.  
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica's latest configurable processor.  ...  Conventional simulation-based verification methodologies that employ assembly programs for testing cannot easily link the diagnostic program to the test-bench for interactive control, consequently resulting  ...  CONFIGURABLE VERIFICATION INFRASTRUCTURE Developing a test-bench for functional verification of a configurable processor is challenging in many ways.  ... 
doi:10.1109/dac.2005.193923 fatcat:tszyzzcz6rglriju7sqcrac53u

Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

Pan Guoteng, Tang Yuxing, Ou Guodong, Luo Li, Yang Qingna
2014 Open Cybernetics and Systemics Journal  
Based on FT-8 multicore processor, we developed a configurable test stimulus acceleration method, loading the test stimulus into memory and L2 cache to speed up the processor instructions fetch, which  ...  Functional verification has become a major challenge in the chip design area. To improve the efficiency of verification, it is necessary to choose appropriate verification method and tools.  ...  INTRODUCTION The increasing complexity of chip design is creating many challenges for verification.  ... 
doi:10.2174/1874110x01408010017 fatcat:dhf5onzjbva6zazoogcqvkzd4m

Methodology for validating Nest Memory Management Unit

Nandhini Rajaiah, Jayakumar Sankarannair, Larry Leitner
2019 EAI Endorsed Transactions on Cloud Systems  
The growing demand for performance makes the processor logic design more complex, thereby making post-silicon validation a critical and complex step in processor development life cycle.  ...  One such unit to cater to newer workloads in recent superscalar processors is the Nest Memory Management Unit (NMMU), a memory management unit for all I/O devices.  ...  ., for his valuable feedback and support in completing this paper.  ... 
doi:10.4108/eai.15-3-2019.162139 fatcat:wnfxgv3bgnakri3pqcuz2pbcoa

Innovative Verification Techniques Used in the Implementation of a Third-Generation 1.1GHz 64b Microprocessor [chapter]

Victor Melamed, Harry Stuimer, David Wilkins, Lawrence Chang, Kevin Normoyle, Sutikshan Bhutani
2002 Lecture Notes in Computer Science  
Verifying the robustness of the cache coherency maintaining parts of the design was one of the main challenges facing the functional verification team.  ...  This paper presents an innovative tool used during the verification of the UltraSPARC #IIIi (TM) processor. UltraSparc #IIIi operates in a multi-processor environment.  ...  In both cases the maximum distance between the chosen address and the sniper address can be configured. Sniper knows which JBUS agents generate the addresses that appear on the bus.  ... 
doi:10.1007/3-540-36135-9_23 fatcat:ek4rb2nwxnh6vnj75xu4y6a6nq

Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation

Shady Copty, Itai Jaeger, Yoav Katz, Michael Vinov
2007 Proceedings - Design Automation Conference  
We report on a method for system-level test case generation. This method relies on dynamic interleaving of scenarios from the core level or sub-system level.  ...  We also describe a tool that implements this method and show how it was used in IBM for system verification of the Xbox 360 chip and Power Management in the Cell processor, as well as verification of the  ...  The system verification organization is faced with the constant challenge of creating and implementing a verification plan for the large number of system configurations.  ... 
doi:10.1109/dac.2007.375290 fatcat:pan26c6mgrh5tayjim3rih5je4

Intelligent interleaving of scenarios

Shady Copty, Itai Jaeger, Yoav Katz, Michael Vinov
2007 Proceedings - Design Automation Conference  
We report on a method for system-level test case generation. This method relies on dynamic interleaving of scenarios from the core level or sub-system level.  ...  We also describe a tool that implements this method and show how it was used in IBM for system verification of the Xbox 360 chip and Power Management in the Cell processor, as well as verification of the  ...  The system verification organization is faced with the constant challenge of creating and implementing a verification plan for the large number of system configurations.  ... 
doi:10.1145/1278480.1278700 dblp:conf/dac/CoptyJKV07 fatcat:fl4b6uswsbee5iz5pocalvowj4

Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems

D. W. Victor, J. M. Ludden, R. D. Peterson, B. S. Nelson, W. K. Sharp, J. K. Hsu, B.-L. Chu, M. L. Behm, R. M. Gott, A. D. Romonosky, S. R. Farago
2005 IBM Journal of Research and Development  
For the system-level verification, a new test-case-generation tool was utilized which allowed for more targeted testing through a deeper knowledge of the system topology.  ...  In parallel with the mainline functional validation, verification of reliability functions and performance attributes also had increased focus for the POWER5 design.  ...  Scope of verification The capability of dynamically switching between ST and SMT modes introduced new challenges to the POWER5 verification team beyond those already addressed for standalone SMT testing  ... 
doi:10.1147/rd.494.0541 fatcat:jnkly5gj3zfphcfjxb5quh2fym

Architectural Trace-Based Functional Coverage for Multiprocessor Verification

Biruk Mammo, Jim Larimer, Matthew Morgan, Dave Fan, Eric Hennenhoefer, Valeria Bertacco
2012 2012 13th International Workshop on Microprocessor Test and Verification (MTV)  
Even then, the quality of the tests can be assured only on one specific design implementation -an undesirable characteristic for test and regression suites that are meant to be used across multiple generations  ...  For an out-of-order multi-processor design, simulation of a detailed model of the design is often required to observe relevant design behaviors for functional coverage.  ...  In the unified trace generated from two processors running this instruction sequence, memory accesses to a common address by the two processors point us to the lock address.  ... 
doi:10.1109/mtv.2012.12 dblp:conf/mtv/MammoLMFHB12 fatcat:hgl2vdznhnbt7ggfmoifqlfkou

Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL [article]

Abhishek Jain, Dr. Hima Gupta, Sandeep Jana, Krishna Kumar
2014 arXiv   pre-print
Quicker Verification requires early development of the verification environment with wider test vectors without waiting for RTL to be available.  ...  Main Keywords are SystemVerilog, SystemC, Transaction Level Modeling, Universal Verification Methodology (UVM), Processor model, Universal Verification Component (UVC), Reference Model.  ...  ACKNOWLEDGMENT The authors would like to specially thank to their management Giuseppe Bonanno (CAD Manager, Imaging Division, and STMicroelectronics) and Antoine Perrin (Manager, SDS Team, STMicroelectronics) for  ... 
arXiv:1408.1150v1 fatcat:exyx5nusjnebpk2wqyn6d6g2ie

Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL

Abhishek Jain, Sandeep Jana, Dr. Hima, Krishna Kumar
2014 International Journal of Advanced Computer Science and Applications  
Quicker Verification requires early development of the verification environment with wider test vectors without waiting for RTL to be available.  ...  In this paper, we are presenting a novel approach of early development of reusable multi-language verification flow, by addressing four major activities of verification - 1.  ...  ACKNOWLEDGMENT The authors would like to specially thank to their management Giuseppe Bonanno (CAD Manager, Imaging Division, and STMicroelectronics) and Antoine Perrin (Manager, SDS Team, STMicroelectronics) for  ... 
doi:10.14569/ijacsa.2014.050212 fatcat:x37gr3vri5gnbjvjw7zcupicfq

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems

J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B.-L. Chu, M. L. Behm, J. R. Baumgartner, R. D. Peterson, J. Abdulhafiz, W. E. Bucy, J. H. Klaus (+13 others)
2002 IBM Journal of Research and Development  
Finally, system-level verification tested multiprocessor coherence and system-level function, including processor-to-I/O communication and validation of multiple hardware configurations.  ...  Multi-unitlevel verification, performed on storage and I/O components as well as on the processor, confirmed architectural compliance for each of the chips and subsystems.  ...  It begins by addressing the verification challenges presented by the complex microarchitecture.  ... 
doi:10.1147/rd.461.0053 fatcat:474llttpkvghngwg4q6veuhvqq

Application Specific Hardware Design Simulation for High Performance Embeddeed System

Ravi Khatwal, Manoj Kumar Jain
2014 International Journal of Computer Applications  
Xilinx provides SDK and XPS tools, XPS tools used for develop complete hardware platform and SDK provides software platform for application creation and verification.  ...  Application specific simulation is challenging task in various real time high performance embedded devices. In this study specific application is implemented with the help of Xilinx.  ...  Processor D-Cache configuration XPS (seefigure 8) used the Base System Builder, and it generated a bit stream for the FPGA.  ... 
doi:10.5120/16834-6599 fatcat:4rbwuni6drdg3lhnidjf4e27fm

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation

Sameh Asaad, José Tierno, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin Parker, Thomas Roewer, Proshanta Saha, Todd Takken
2012 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12  
This paper discusses the challenges for constructing such largescale FPGA platforms, including design partitioning, clocking & synchronization, and debugging support, as well as our approach for addressing  ...  In this paper, we describe a cycle-accurate and cyclereproducible large-scale FPGA platform that is designed from the ground up to accelerate logic verification of the Bluegene/Q compute node ASIC, a multi-processor  ...  Existing solutions for accelerating the logic verification problem involve either generalized systems capable of addressing any digital design, or specialized solutions achieving maximum performance targeting  ... 
doi:10.1145/2145694.2145720 dblp:conf/fpga/AsaadBBHKPRSTT12 fatcat:dtcqzyjhizg3tejrhxgx7wj3x4
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