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Address-branch correlation: A novel locality for long-latency hard-to-predict branches

Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zhou
2008 High-Performance Computer Architecture  
This paper presents a novel program locality that can be exploited to handle long-latency hard-topredict branches.  ...  If a hard-to-predict branch depends on such stable data, the address of the data rather than the data value is sufficient to determine the branch outcome.  ...  Acknowledgement We thank the anonymous reviewers for their valuable comments on improving our paper.  ... 
doi:10.1109/hpca.2008.4658629 dblp:conf/hpca/GaoMDZ08 fatcat:jbucklxtpjguhjsaacmgu6slni

CVP

Mingxing Tan, Xianhua Liu, Tong Tong, Xu Cheng
2012 Proceedings of the 26th ACM international conference on Supercomputing - ICS '12  
The value pattern reflects the pattern regularity of the value correlation, and thus significantly improves the prediction accuracy even in the case of deep pipeline stage or long memory latency.  ...  The key of CVP prediction is to use the compilerguided value pattern as the correlated information to hint the dynamic predictor.  ...  The FT contains a serial of branch pc, i.e., the address of hard-to-predict branches.  ... 
doi:10.1145/2304576.2304593 dblp:conf/ics/TanLTC12 fatcat:wwnlvk3burfrdd34amejyhucg4

An Energy-Efficient Branch Prediction with Grouped Global History

Mingkai Huang, Dan He, Xianhua Liu, Mingxing Tan, Xu Cheng
2015 2015 44th International Conference on Parallel Processing  
The state-of-the-art branch predictors, such as the perceptron and TAGE predictors, leverage novel prediction algorithms to explore longer branch history for higher prediction accuracy.  ...  Unlike existing branch predictors that make use of a unified global history for prediction, GGH divides the global history into a set of subgroups such that the interference resulted by frequently executed  ...  ACKNOWLEDGEMENTS We are particularly grateful to Teacher Dong Tong for his great suggestions on this work. We would like to thank the anonymous reviewers for their constructive feedback.  ... 
doi:10.1109/icpp.2015.23 dblp:conf/icpp/HuangHLTC15 fatcat:2rgholbqjvcrrksmnxyuuw4d2i

Online data center traffic classification based on inter-flow correlations

Meriem Amina SI Saber, Mehdi Ghorbani, Abdolkhalegh Bayati, Kim-Khoa Nguyen, Mohamed Cheriet
2020 IEEE Access  
In this paper, we propose a novel correlation-based algorithm following a cost-sensitive approach combined with a Bagged Random Forest (BRF) ensemble algorithm, to address the inter-class imbalance problem  ...  In this strategy, a new method based on Reverse k-Nearest Neighbors (RkNN) is proposed to capture the rebalancing weights expressing inter-flow correlations, in order to perform an online classification  ...  ACKNOWLEDGMENT The authors would like to thank Chuan Pham for his help.  ... 
doi:10.1109/access.2020.2983605 fatcat:rehfafnbpvbjteqj3pkvnt6u5y

Detecting global stride locality in value streams

Huiyang Zhou, Jill Flanagan, Thomas M. Conte
2003 SIGARCH Computer Architecture News  
A novel prediction scheme, called the gDiff predictor, is designed to exploit one special and most common case of this computational model, the stridebased computation, in the global value history.  ...  We also show that the global stride locality detected by gDiff in load address streams provides strong capabilities in predicting load addresses (coverage 63% and accuracy 86%) and in predicting addresses  ...  The reason for the low predictability is due to the hard-to-predict generational values and the long computation chain of these hard-to-predict values.  ... 
doi:10.1145/871656.859656 fatcat:zmzmd4w6nrfrlaysev7rqsjd2y

Detecting global stride locality in value streams

Huiyang Zhou, Jill Flanagan, Thomas M. Conte
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
A novel prediction scheme, called the gDiff predictor, is designed to exploit one special and most common case of this computational model, the stridebased computation, in the global value history.  ...  We also show that the global stride locality detected by gDiff in load address streams provides strong capabilities in predicting load addresses (coverage 63% and accuracy 86%) and in predicting addresses  ...  The reason for the low predictability is due to the hard-to-predict generational values and the long computation chain of these hard-to-predict values.  ... 
doi:10.1145/859654.859656 fatcat:pwmkgm63ajh4hjacbvlmcwopni

Detecting global stride locality in value streams

Huiyang Zhou, Jill Flanagan, Thomas M. Conte
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
A novel prediction scheme, called the gDiff predictor, is designed to exploit one special and most common case of this computational model, the stridebased computation, in the global value history.  ...  We also show that the global stride locality detected by gDiff in load address streams provides strong capabilities in predicting load addresses (coverage 63% and accuracy 86%) and in predicting addresses  ...  The reason for the low predictability is due to the hard-to-predict generational values and the long computation chain of these hard-to-predict values.  ... 
doi:10.1145/859618.859656 fatcat:z7f52ggk5vdzbiuvrpjxfg4agi

Branch Predicting with Sparse Distributed Memories [article]

Ilias Vougioukas, Andreas Sandberg, Nikos Nikoleris
2021 arXiv   pre-print
The key idea described in this work is to use hyperdimensional computing and sparse distributed memory principles to create a novel branch predictor that can deliver complex predictions for a fraction  ...  To improve instruction-level parallelism, the processor core needs to fetch and decode multiple instructions per cycle and has come to rely on incredibly accurate branch prediction.  ...  Latency constraints are important as the branch predictor lies on the critical path and needs to provide a prediction almost as soon as the branch address is known.  ... 
arXiv:2110.09166v1 fatcat:cjuu5fee5rhlvoj6kklaacnb2e

A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

Vasilios Kelefouras, Karim Djemame
2019 Journal of Supercomputing  
Firstly, by applying a novel register blocking algorithm and a novel loop tiling algorithm and secondly, by computing the maximum and minimum ET/E values for each optimization set.  ...  A novel methodology is presented reducing the exploration space of six code optimizations by many orders of magnitude.  ...  Acknowledgements This work is partly supported by the European Commission under H2020-ICT-20152 contract 687584 -Transparent heterogeneous hardware Architecture deployment for eNergy Gain in Operation  ... 
doi:10.1007/s11227-019-02880-z fatcat:gscntfzzh5ddphjhfuzdba74ci

Mining block correlations to improve storage performance

Zhenmin Li, Zhifeng Chen, Yuanyuan Zhou
2005 ACM Transactions on Storage  
C-Miner is a direct application of a frequent-sequence mining algorithm with a few modifications; compared with C-Miner, C-Miner* is redesigned for mining block correlations by making concessions for the  ...  In this article, we propose two algorithms, C-Miner and C-Miner*, that use a data mining technique called frequent sequence mining to discover block correlations in storage systems.  ...  We are also grateful to Professor Jiawei Han and his student Xifeng Yan for their help with the CloSpan algorithm and insightful discussions.  ... 
doi:10.1145/1063786.1063790 fatcat:xnzli6qgtneprhwaxsfcpsn6u4

EXACT

Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg
2010 Proceedings of the 7th ACM international conference on Computing frontiers - CF '10  
For a branch of this type, there is a unique dynamic instance of the branch for each unique combination of producer-load addresses.  ...  We propose that stores to the memory addresses on which a dynamic branch depends, directly update its prediction in the predictor.  ...  ACKNOWLEDGMENTS We thank the anonymous reviewers for their valuable feedback. This research was supported by NSF grants CCF-0702632 and CCF-0916481, SRC grant 2007-HJ-1594, and an Intel gift.  ... 
doi:10.1145/1787275.1787321 dblp:conf/cf/Al-OtoomFR10 fatcat:325g7u7kujdobkac5klmrwh6tm

An energy-efficient branch prediction technique via global-history noise reduction

Zichao Xie, Dong Tong, Xu Cheng
2013 International Symposium on Low Power Electronics and Design (ISLPED)  
This paper proposes a novel branch prediction technique called History Artificially Selected (HAS) prediction.  ...  Through using a tournament mechanism, HAS prediction selectively uses the modified branch history to eliminate the history noise interferences and retain those useful history correlations at the same time  ...  In this paper, we propose a novel branch prediction technique called History Artificially Selected (HAS) prediction.  ... 
doi:10.1109/islped.2013.6629296 dblp:conf/islped/XieTC13 fatcat:ggdixrwtkvg3dftwratljbbnu4

B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz, Daniel Jimenez
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
We propose B-Fetch: a data prefetcher driven by branch prediction and effective address value speculation.  ...  These concerns point to the need for a light-weight prefetcher with high accuracy.  ...  In the presence of a long-latency load, a typical core would idle, once the ROB is full, saving energy.  ... 
doi:10.1109/micro.2014.29 dblp:conf/micro/KadjoKSPGJ14 fatcat:rbk4bf4dfrfjnaxawb2f2yeqtu

Designing a time predictable memory hierarchy for single-path code

Bekim Cilku, Peter Puschner
2015 ACM SIGBED Review  
Trustable Worst-Case Execution-Time (WCET) bounds are a necessary component for the construction and verification of hard real-time computer systems.  ...  The single-path conversion overcomes this difficulty by transforming all unpredictable branch alternatives in the code to a sequential code structure with a single execution trace.  ...  The long latency of memory accesses is one of the key performance bottlenecks of contemporary computer systems.  ... 
doi:10.1145/2782753.2782755 fatcat:yczv4adi45hapg3vbujdmtu3dy

Leveraging speculative architectures for run-time program validation

Juan Carlos Martinez Santos, Yunsi Fei
2008 2008 IEEE International Conference on Computer Design  
Due to good code locality of the executable programs and effectiveness of branch prediction, the frequency of run-time control flow validations against the secure off-chip memory is low.  ...  In this paper, we propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation.  ...  By utilizing the existing branch target address prediction mechanism, our mechanism achieves negligible performance overhead even with a long latency for accessing the FRS. VI.  ... 
doi:10.1109/iccd.2008.4751907 dblp:conf/iccd/SantosF08 fatcat:qscfzf6inbe4hfn4hxo37pmn3u
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