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Energy-efficient adaptive wireless NoCs architecture

Dominic DiTomaso, Avinash Kodi, David Matolak, Savas Kaya, Soumyasanta Laha, William Rayess
2013 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)  
In this paper, we propose an adaptable wireless Network-on-Chip architecture (A-WiNoC) that uses adaptable and energy efficient wireless transceivers to improve network power and throughput by adapting  ...  Scalable Network-on-Chip (NoC) designs are quickly becoming the standard communication framework to replace bus-based networks.  ...  Network-on-Chip (NoC) designs are the response to the limitations of bus-based networks [1] . NoCs can provide high bandwidth communication for CMPs.  ... 
doi:10.1109/nocs.2013.6558400 dblp:conf/nocs/DiTomasoKMKLR13 fatcat:qwkn2f332nf4dbzoldkfagtp2e

2018 Index IEEE Transactions on Computers Vol. 67

2019 IEEE transactions on computers  
., þ, TC Sept. 2018 1231-1245 First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip.  ...  ., þ, TC Sept. 2018 1231-1245 First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip.  ... 
doi:10.1109/tc.2018.2882120 fatcat:j2j7yw42hnghjoik2ghvqab6ti

A survey of research and practices of Network-on-chip

Tobias Bjerregaard, Shankar Mahadevan
2006 ACM Computing Surveys  
This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network and link; to explain and structure the fundamental concepts.  ...  Even though on-chip wires are cheap in comparison with off-chip wires, on-chip communication is becoming still more costly, in terms of both power and speed.  ...  Also our grateful thanks to professor Axel Jantsch (KTH -Stockholm, Sweden) and Andrei Radulescu (Phillips -Eindhoven, Netherlands) for their valuable review of the survey as it was closing in on its final  ... 
doi:10.1145/1132952.1132953 fatcat:kpaihucc7rbqfg2ujtg7xubbqq

A case for dynamic frequency tuning in on-chip networks

Asit K. Mishra, Ravi Iyer, Reetuparna Das, N. Vijaykrishnan, Soumya Eachempati, Chita R. Das
2009 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42  
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for multicores/CMPs.  ...  to 70% at high load) in EDP.  ...  ACKNOWLEDGEMENTS We would like to thank the anonymous reviewers for their reviews and comments in improving this paper.  ... 
doi:10.1145/1669112.1669151 dblp:conf/micro/MishraIDVED09 fatcat:dpjku5um6fc3tbcpkque473qgy

Adaptive Routing on the New Switch Chip for IBM SP Systems

Bulent Abali, Craig B. Stunkel, Jay Herring, Mohammad Banikazemi, Dhabaleswar K. Panda, Cevdet Aykanat, Yucel Aydogan
2001 Journal of Parallel and Distributed Computing  
Switch2 offers significant enhancements over the existing SP switch chips by incorporating advances in both VLSI technology and interconnection network research.  ...  We describe the adaptive source routing architecture of the Switch2 chip which is a unique feature of this chip.  ...  This architecture is not only backward compatible with previous generations of SP networks but it also allows a mix of adaptive and oblivious traffic to coexist in the same network.  ... 
doi:10.1006/jpdc.2001.1747 fatcat:2n2ogpi7ffezzd6gfycmw7ue5y

Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation

Xin Zhan, Jianhao Chen, Edgar Sanchez-Sinencio, Peng Li
2019 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
(VRs), to on-chip switching VRs, and finally to networks of distributed on-chip linear VRs.  ...  static two-stage voltage regulation using off-chip and on-chip switching VRs.  ...  VRs, and finally to networks of distributed on-chip linear VRs.  ... 
doi:10.1109/tvlsi.2019.2923911 fatcat:bizdu2xy4bf2pjyobzuk7l53c4

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing

Terrence S.T. Mak, Pete Sedcole, Peter Y.K. Cheung, Wayne Luk, K.P. Lam
2007 First International Symposium on Networks-on-Chip (NOCS'07)  
Implementing dynamic routing on a network-on-chip (NoC) platform requires a design that provides highly efficient optimal path computation coupled with reduced area and power consumption.  ...  In this paper, we present a hybrid analog-digital routing network design that enables efficient dynamic routing on an NoC architecture.  ...  The traffic load injected into the network is smaller than the critical traffic load. Both distributions are having the peak on latencies between zero and 500 cycles.  ... 
doi:10.1109/nocs.2007.2 dblp:conf/nocs/MakSCLL07 fatcat:mljkrgp7qffapatbrb4belpa7i

A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control

Yong-Bin Kim, Kyung Ki Kim, James Doyle
2007 2007 IEEE International Symposium on Circuits and Systems  
A fully digital self-adjusting high efficiency power supply system has been developed based on an FSM control scheme.  ...  slacktime detector, and provides a substantially constant minimum-supply voltage for digital processors to properly operate at a given frequency with regard to different processvoltage-temperature (PVT) and load  ...  They in turn impact the performance of circuit since they generate deviations in MOSFET drive current, resulting in propagation delay distributions of the critical path across a chip.  ... 
doi:10.1109/iscas.2007.378253 dblp:conf/iscas/KimKD07 fatcat:izdneue3sjdezavutxr5rkyss4

An adaptive on-chip voltage regulation technique for low-power applications

N. Dragone, A. Aggarwal, L.R. Carley
2000 ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)  
in mixed swing QuadRail.  ...  In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process induced delay variations  ...  On the other hand an analysis of the delays of groups of critical path replicas on the same chip and in close proximity, showed that this variance is reduced to 1-2ns.  ... 
doi:10.1109/lpe.2000.155247 fatcat:gzmkaeqbnrcr5prnqnliejex2m

An adaptive on-chip voltage regulation technique for low-power applications

Nicola Dragone, Akshay Aggarwal, L. Richard Carley
2000 Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00  
in mixed swing QuadRail.  ...  In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process induced delay variations  ...  On the other hand an analysis of the delays of groups of critical path replicas on the same chip and in close proximity, showed that this variance is reduced to 1-2ns.  ... 
doi:10.1145/344166.344185 dblp:conf/islped/DragoneAC00 fatcat:37vtbhnhhbap7kezc7g2l57i4e

Network-based computing

H. Sarbazi-Azad, L.M. Mackenzie
2007 Journal of computer and system sciences (Print)  
Virtual channels play a critical role, particularly in interconnection networks based on wormhole routing.  ...  At the other end of the scale are network on chip (NoC) systems.  ... 
doi:10.1016/j.jcss.2007.02.012 fatcat:z6pbh5x2sjbhzjmkydgao7ooza

Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures

Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Khalid Latif, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2012 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip  
a 3D NUCA L2 Cache for CMPs. 7 • It does not allow concurrent communication in the third dimension. • In a high network load, the probability of contention and blocking critically increases.  ...  network from implementing adaptive routing algorithms.  ... 
doi:10.1109/nocs.2012.28 dblp:conf/nocs/RahmaniV0LPT12 fatcat:tttxmyay3zaczci5nc3o23544y

Multilevel fluidic flow control in a rotationally-driven polyester film microdevice created using laser print, cut and laminate

Yiwen Ouyang, Jingyi Li, Christopher Phaneuf, Paul S. Riehl, Craig Forest, Matthew Begley, Doris M. Haverstick, James P. Landers
2016 Lab on a Chip  
A simple and cost-effective polyester toner microchip was fabricated to provide fluid handling on a centrifugal platform.  ...  Begley) 50 express gratitude to the NIH for support on exploration of passive valving approaches for microfluidic systems (NIH R01 KK1103).  ...  network shown in Figure 1A .  ... 
doi:10.1039/c5lc01332a pmid:26675027 fatcat:btwstobozfg7vfawk5ga7iwjdq

Cooperation between Distributed Power Modules for SoC Power Management

Po-Chiun HUANG, Shin-Jie HUANG, Po-Hsiang LAN
2016 IEICE transactions on electronics  
The key controller is a mixed-signal estimator that executes the intelligent procedures, like real-time swap the power module depending on its loading and healthy condition, automatically configure the  ...  In addition, dedicated power sources for critical circuit blocks can achieve better signal integrity.  ...  The authors would like to thank the Chip Implementation Center (CIC), Taiwan, for chip fabrication service, and Dr. J.-H. Tsai for his technological assistance.  ... 
doi:10.1587/transele.e99.c.606 fatcat:efdb4kkhhbegjevnscfgptoxni

RAFT: A router architecture with frequency tuning for on-chip networks

Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi Iyer, N. Vijaykrishnan, Chita R. Das
2011 Journal of Parallel and Distributed Computing  
With increasing number of cores being integrated on a single die, Network-on-Chips (NoCs) have become the de-facto standard in providing scalable communication backbones for these multi-core chips.  ...  to 70% at high load) in EDP.  ...  Acknowledgments We would like to thank the anonymous reviewers for their reviews and comments in improving this paper.  ... 
doi:10.1016/j.jpdc.2010.09.005 fatcat:dvhpez5scfguxdqjkm6m7eqosq
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