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Scheduling analysis of time-constrained dual-armed cluster tools
2003
IEEE transactions on semiconductor manufacturing
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Cluster tools, each of which consists of several singlewafer processing chambers and a wafer handling robot, have been increasingly used for diverse wafer fabrication processes. ...
We address the scheduling problem for such time-constrained dual-armed cluster tools that have diverse wafer flow patterns. ...
CONCLUSION We have examined a scheduling problem of dual-armed cluster tools with various flow patterns under wafer delay constraints. ...
doi:10.1109/tsm.2003.815203
fatcat:jq65hirb6bbhvlw7rbmtt3um74
Virtual Control
2004
IEEE robotics & automation magazine
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A cluster tool usually has six or eight PMs, a cooler (CL), an aligner (AL), two loadlocks (LLs), and a TM based on a robot ...
Dong-Hwan Hwang for his work on 3-D graphic modeling of a cluster tool.
Keywords Cluster tool, semiconductor manufacturing, control software, virtual model, verification. ...
Acknowledgments This work was supported in part by Korea Science Foundation's Grant 98-0200-08-01-2 and Jusung Engineering Ltd., Korea. The authors thank Mr. ...
doi:10.1109/mra.2004.1337825
fatcat:efilt22ejrgq7np4ja75zhsxlm
Scheduling of Single-Arm Cluster Tools with Residency Time Constraints and Chamber Cleaning Operations
2021
Applied Sciences
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Wafer residency time constraints and chamber cleaning operations make the scheduling problem of cluster tools more challenging. ...
To ensure wafer quality, engineers have to impose wafer residency time constraints and chamber cleaning operations on cluster tools; this has been widely used in semiconductor manufacturing. ...
Conflicts of Interest: The authors declare no conflict of interest. ...
doi:10.3390/app11199193
fatcat:k2goriblrnf5xp6l6z73m6qrzu
On scheduling a photolithography area containing cluster tools
2018
Computers & industrial engineering
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2017 pre-print arXiv:1708.09488v1 fatcat:btmf73wg4fhvlg3e2woidfn5p4Other Versions
In this paper, we present a model for optimizing the scheduling of the photolithography process in the presence of both individual and cluster tools. ...
delays in a wafer fab. ...
The research can be extended to deal with finding a solution for minimizing other objectives like minimizing the total number of tardy jobs, minimizing maximum lateness, or to extend the research to investigate ...
doi:10.1016/j.cie.2018.05.036
fatcat:xtez43lb75ebdk65gn7udqcl34
Using simulation and hybrid sequencing optimization for makespan reduction at a wet tool
2012
Proceedings Title: Proceedings of the 2012 Winter Simulation Conference (WSC)
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When rigid scheduling rules apply to wet tools, the development of Cycle Time (CT) optimization strategies becomes a relevant challenge. ...
detailed schedules in short computational times. ...
The model developed by Mauer and Schelasin (1993) is conceived as a flexible model which can be easily adapted to mimic the behavior of any type of integrated tools, such as cluster tools. ...
doi:10.1109/wsc.2012.6465086
dblp:conf/wsc/RotondoGY12
fatcat:ssid2dkqnzhghk6y3nv42gtnna
Transient Process Optimization for Dual-Arm Cluster Tools With Wafer Revisiting
2021
IEEE Access
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[24] present an adaptive scheduling approach to cluster tools with tight wafer residency time constraints and large processing time variations. ...
Thus, it requires that the schedule for cluster tools should possess sufficient adaptiveness and robustness [11] - [15] . ...
doi:10.1109/access.2021.3069888
fatcat:ops7gpuznna3djmtty6672jnnq
Impact of Parameter Variations on Circuits and Microarchitecture
2006
IEEE Micro
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A significant number of lithography-related variability problems stem from the stepper. The step-and-repeat process exposes each region of the wafer at different times. ...
These variations are the result of within-wafer processing differences such as resist thickness variation, stepper lens focus aberrations, and uneven doping. ...
doi:10.1109/mm.2006.122
fatcat:2qayw5i7nfegrbz7yzsv3caoa4
Test and Design-for-Testability Solutions for 3D Integrated Circuits
2014
IPSJ Transactions on System LSI Design Methodology
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of probe access for wafers, test access in stacked dies, yield enhancement, and new defects arising from unique processing steps. ...
of die wrappers, test scheduling, and access to dies and inter-die interconnects; (iii) interconnect testing in interposer-based 2.5D ICs; (iv) fault diagnosis and TSV repair; (v) cost modeling and test-flow ...
This approach greatly reduces the effect of delay variations in gates and interconnects due to random process variations. The results of this simulation are shown in Fig. 8 . ...
doi:10.2197/ipsjtsldm.7.56
fatcat:56jqb2gwcne5flmqg3gt27ttbm
A Review of Data Mining Applications in Semiconductor Manufacturing
2021
Processes
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For decades, industrial companies have been collecting and storing high amounts of data with the aim of better controlling and managing their processes. ...
The size of the semiconductors signifies a high number of units can be produced, which require huge amounts of data in order to be able to control and improve the semiconductor manufacturing process. ...
the time-to-market for more advanced, innovative, and gradually elaborate designs and processes demands for process tools and wafers to be examined and verified with up-to-date measurement systems and ...
doi:10.3390/pr9020305
fatcat:jyxg4mt3gvbahnu3snh4i3rxvm
2020 Index IEEE Transactions on Automation Science and Engineering Vol. 17
2020
IEEE Transactions on Automation Science and Engineering
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., +, TASE Jan. 2020 166-176
Cluster tools
Adaptive Scheduling of Cluster Tools With Wafer Delay Constraints and
Process Time Variation. ...
., +, TASE July 2020 1237-1249 Adaptive Scheduling of Cluster Tools With Wafer Delay Constraints and Process Time Variation. ...
., +, TASE July 2020 1237 -1249 Comments and Corrections to "Process Mining to Discover Shoppers' Pathways at a Fashion Retail Store Using a WiFi-Base Indoor Positioning System" [Oct 17 1786 [Oct 17 ...
doi:10.1109/tase.2020.3037603
fatcat:kyt63444lfc45amrjebyjw34qu
Predictive and Reactive Scheduling for a Critical Machine of a Production System
2014
Advanced Materials Research
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Having Mean Time To First Failure, and Mean Time of Repair a disturbance robust predictive schedule is generated using rule: Minimal Impact of Disturbed Operation on the Schedule. ...
In the paper a production model with failures is presented where successive failure-free times are supposed to have normal distributions and are followed by normally distributed times of repairs. ...
Acknowledgments The authors would like to acknowledge Cor Hurkens for his valuable comments and Roel Boumen and Maarten van Bree for their help with the case. ...
doi:10.4028/www.scientific.net/amr.1036.909
fatcat:3ujweobndjgl7mqotcqrxfyypy
2020 Index IEEE Transactions on Systems, Man, and Cybernetics: Systems Vol. 50
2020
IEEE Transactions on Systems, Man & Cybernetics. Systems
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The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. ...
The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. ...
., +, TSMC Dec. 2020 5317-5329 Cluster tools Multiobjective Scheduling of Dual-Blade Robotic Cells in Wafer Fabrica-tion. ...
doi:10.1109/tsmc.2021.3054492
fatcat:zartzom6xvdpbbnkcw7xnsbeqy
The life and times of the Savings Method for Vehicle Routing Problems
2009
ORiON
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savings method has played in the investigation of VRPs with additional constraints. ...
This paper provides the historical background to the development of the savings method and subsequent proposed variations to the basic savings formula and other improvements, and then charts the role the ...
Pearn et al. (2004) investigated the wafer probing scheduling problem (WPSP), a variation of the parallel-machine scheduling problem, to sequence families of jobs on identical parallel machines with due ...
doi:10.5784/25-2-78
fatcat:lsz64ftkajgf3m5hgsrt7r57ci
Adaptive Abstraction-Level Conversion Framework for Accelerated Discrete-Event Simulation in Smart Semiconductor Manufacturing
2020
IEEE Access
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Typical DE fab models use random variables that follow certain distributions to define model's operation parameters, such as a wafer-processing time of tool models or wafer-lifting (or break) time of operator ...
A lot's cycle time is the difference between the generation time and the completion time of all steps of wafer processing. ...
doi:10.1109/access.2020.3022275
fatcat:k4kooxkm4ze7xjohpo4s6dfb5e
A two-stage coupled algorithm for an integrated maintenance planning and flowshop scheduling problem with deteriorating machines
2015
Journal of Scheduling
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The integrated approach models the interdependencies between maintenance and scheduling decisions in highly coupled processes such as wafer fabrication in the semiconductor manufacturing. ...
Deterioration of machines over time decreases production capacity. ...
In this process, wafer lots (production jobs) flow through the system, requiring several operations to be performed by various cluster tools (machines) (Kumar and Kumar, 2001) . ...
doi:10.1007/s10951-015-0416-2
fatcat:ieno2gxpmjg3de7ohvo3nb3rdy
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