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Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration

Gianluca Durelli, Fabrizio Spada, Riccardo Cattaneo, Christian Pilato, Danilo Pau, Marco D. Santambrogio
2014 2014 IEEE International Parallel & Distributed Processing Symposium Workshops  
We exploit partial dynamic reconfiguration to adapt the hardware to the specific part of the image under analysis.  ...  In this paper we propose a hardware implementation of the raytracing algorithm, which is a method for rendering 3D scenes.  ...  Acknowledgments This work was partially funded by the European Commission in the context of the FP7 FASTER project (#287804).  ... 
doi:10.1109/ipdpsw.2014.31 dblp:conf/ipps/DurelliSCPPS14 fatcat:2mp22qiczndxjda2fndlepf53q

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board

F. Spada, A. Scolari, G.C. Durelli, R. Cattaneo, M.D. Santambrogio, D. Sciuto, D.N. Pnevmatikatos, G.N. Gaydadjiev, O. Pell, A. Brokalakis, W. Luk, D. Stroobandt (+1 others)
2014 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications  
The novelty of the framework relies in the fact that the partial dynamic reconfiguration, which FPGA devices can exploit, is seen as a first class citizen throughout the whole design flow.  ...  This work reports a case study in which the FASTER toolchain has been used to port a raytracer application onto the STM Spear prototyping embedded platform.  ...  ACKNOWLEDGMENTS This work was partially funded by the European Commission in the context of the FP7 FASTER project (#287804).  ... 
doi:10.1109/ispa.2014.26 dblp:conf/ispa/SpadaSDCSSPGPBLSP14 fatcat:wqq4gfpomvf2jdfqoeqb55ot6a

Evaluating a High-Level Parallel Language (GpH) for Computational GRIDs

A.D. Al Zain, P.W. Trinder, G.J. Michaelson, H.-W. Loidl
2008 IEEE Transactions on Parallel and Distributed Systems  
of GpH, to produce the first high-level DSM parallel language implementation for computational GRIDs.  ...  The high-level language, Glasgow parallel Haskell (GpH), abstracts over the architectural complexities of the computational GRID, and we have developed GRID-GUM2, a sophisticated grid-specific implementation  ...  Harness [22] (Heterogeneous Adaptable Reconfigurable Networked Systems) focuses on dynamic, adaptive resource management and even provides facilities for dynamically splitting and merging of distributed  ... 
doi:10.1109/tpds.2007.70728 fatcat:p6kuy3eszbejda5so7ztqzbqg4

3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores

Randy Morris, Avinash Karanth Kodi, Ahmed Louri
2012 2012 IEEE 30th International Conference on Computer Design (ICCD)  
We propose to develop a multi-layer NIs that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links.  ...  In this paper, we propose to combine NIs with with 3D stacking to develop a scalable, reconfigurable, powerefficient and high-performance interconnect for future many-core systems called 3D-NoC.  ...  ACKNOWLEDGMENT This research was partially supported by NSF awards, ECCS-0725765, CCF-0915537, CCF-0915418, CCF-1054339 (CAREER) and ECCS-1129010 and by the IR/D program while Ahmed Louri was serving at  ... 
doi:10.1109/iccd.2012.6378672 dblp:conf/iccd/MorrisKL12 fatcat:47a42v67q5hl7njho2ixqu2c34

Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration

Randy W. Morris, Avinash Karanth Kodi, Ahmed Louri, Ralph D. Whaley
2014 IEEE transactions on computers  
To maximize performance, we also propose an efficient reconfiguration algorithm that dynamically reallocates channel bandwidth by adapting to traffic fluctuations.  ...  As throughput, scalability, and energy efficiency in network-on-chips (NoCs) are becoming critical, there is a growing impetus to explore emerging technologies for implementing NoCs in future multicore  ...  ACKNOWLEGEMENTS This work was partially supported in part by the US National Science Foundation grants ECCS-0725765, CCF-0953398, CCF-0915418, CCF-1054339 (CAREER), and ECCS-1129010.  ... 
doi:10.1109/tc.2012.183 fatcat:bvgbw2ngovenzip3kahpyh2wwi

dReDBox: A Disaggregated Architectural Perspective for Data Centers [chapter]

Nikolaos Alachiotis, Andreas Andronikakis, Orion Papadakis, Dimitris Theodoropoulos, Dionisios Pnevmatikatos, Dimitris Syrivelis, Andrea Reale, Kostas Katrinis, George Zervas, Vaibhawa Mishra, Hui Yuan, Ilias Syrigos (+4 others)
2018 Hardware Accelerators in Data Centers  
Memory and hardware accelerators can be dynamically assigned to processing units to boost application performance, while high-speed, low-latency electrical and optical interconnect is a prerequisite for  ...  [8] present DyRACT, an FPGA-based compute platform with support for partial reconfiguration at runtime using a static PCIe interface.  ...  The DyRACT implementation is targeting Virtex 6 and Virtex 7 FPGAs, while a video-processing application that employs multiple partial bitstreams is used as a case study for validation and evaluation purposes  ... 
doi:10.1007/978-3-319-92792-3_3 fatcat:3aleh7wb2jfu5fhriswistv5oy

Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration

Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li
2014 2014 IEEE 32nd International Conference on Computer Design (ICCD)  
In this paper, we propose an architectural design to dynamically reconfigure the cache block size for a MLC STT-RAM last-level cache.  ...  The use of STT-RAM as on-chip caches has been widely studied.  ...  , realtime raytracing and video encoding.  ... 
doi:10.1109/iccd.2014.6974672 dblp:conf/iccd/WangRWBL14 fatcat:e3oibprhrbfydpyt26stxezaa4

Reconfigurable Intelligent Surfaces for Wireless Communications: Principles, Challenges, and Opportunities [article]

Mohamed A. ElMossallamy, Hongliang Zhang, Lingyang Song, Karim G. Seddik, Zhu Han, Geoffrey Ye Li
2020 arXiv   pre-print
We describe the working principles of reconfigurable intelligent surfaces (RIS) and elaborate on different candidate implementations using metasurfaces and reflectarrays.  ...  Recently there has been a flurry of research on the use of reconfigurable intelligent surfaces (RIS) in wireless networks to create smart radio environments.  ...  use the partial channel information to infer good RIS configurations.  ... 
arXiv:2005.00938v1 fatcat:hvhxtnhrjbhs7kk5h2w657k4gi

On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors

Mariusz Grad, Christian Plessl
2012 International Journal of Reconfigurable Computing  
While this customization process could be performed during runtime in order to adapt the CPU to the currently executed workload, this use case has been hardly investigated.  ...  Reconfigurable instruction set processors provide the possibility of tailor the instruction set of a CPU to a particular application.  ...  Instruction Implementation. Once the project is created it can be used to generate the partial reconfiguration bitstream representing the FPGA implementation of the custom instruction.  ... 
doi:10.1155/2012/418315 fatcat:gxunfpghyja37h7knhtcaoik7q

Modelling Machine Tools using Structure Integrated Sensors for Fast Calibration

2018 Journal of Manufacturing and Materials Processing  
The development is tested through simulation of the sensor setup based on raytracing and Monte-Carlo techniques.  ...  Monitoring of the relative deviation between commanded and actual tool tip position, which limits the volumetric performance of the machine tool, enables the use of contemporary methods of compensation  ...  implemented the virtual sensor setup; All authors contributed to writing the paper.  ... 
doi:10.3390/jmmp2010014 fatcat:cuzy4sdfwnezzlqnjwqeg7bbhy

Phase-based adaptive recompilation in a JVM

Dayong Gu, Clark Verbrugge
2008 Proceedings of the sixth annual IEEE/ACM international symposium on Code generation and optimization - CGO '08  
Phases are then used to guide adaptive recompilation choices, improving performance. We develop both an offline implementation based on trace data and a self-contained online version.  ...  Our design makes use of a lightweight, low-level profiling mechanism to detect high-level, variable length phases in program execution.  ...  Program phase information can be used to locate stable or repetitive periods of execution at runtime, and has been incorporated into various adaptive optimizations and designs for dynamic system reconfiguration  ... 
doi:10.1145/1356058.1356062 dblp:conf/cgo/GuV08 fatcat:yv3maomyxbe7hi6wgr7bhmekfe

Multi-Camera Active-Vision for Markerless Shape Recovery of Unknown Deforming Objects

Evgeny Nuger, Beno Benhabib
2018 Journal of Intelligent and Robotic Systems  
The algorithm automatically adapts to the quantity of tracking data available and changes in the object's dynamics.  ...  This thesis proposes a multi-camera active-vision reconfiguration system which selects camera poses online to improve the shape recovery of a priori unknown, markerless, deforming objects in dynamic environments  ...  An experimental implementation of dynamic dispatching method was presented in [150] .  ... 
doi:10.1007/s10846-018-0773-0 fatcat:hv6hpzpb7rgkjnbdzywzm573de

Designing highly flexible virtual machines: the JnJVM experience

Gaël Thomas, Nicolas Geoffray, Charles Clément, Bertil Folliot
2008 Software, Practice & Experience  
The main contributions of this paper are the following: • Design and implementation of a minimal, dynamically adaptable execution environment, the Micro Virtual Machine.  ...  As far as we know, there is no other work that tries to build a runtime dedicated to the construction of dynamically adaptable systems. • Design and implementation of the JnJVM, a flexible Java Virtual  ...  The main originality of the JnJVM is the use of MVM components which enable their dynamic adaptation.  ... 
doi:10.1002/spe.887 fatcat:uykjtjfjrnfetb3pdfcs4cppli

Energy-efficient interconnect via Router Parking

A. Samih, Ren Wang, A. Krishna, C. Maciocco, C. Tai, Y. Solihin
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
Further, we propose an adaptive policy to choose between the two algorithms at run-time.  ...  We evaluate our algorithms using both synthetic traffic as well as real workloads taken from SPEC CPU2006 and PARSEC 2.1 benchmark suites.  ...  This is why we need an adaptive design that can choose either one dynamically, based on the run-time network con-ditions.  ... 
doi:10.1109/hpca.2013.6522345 dblp:conf/hpca/SamihWKMTS13 fatcat:nw7jjrza2zfmdbekdkob7hpgny

Efficient virtual machine support of runtime structural reflection

Francisco Ortin, Jose Manuel Redondo, J. Baltasar García Perez-Schofield
2009 Science of Computer Programming  
Increasing trends towards adaptive, distributed, generative and pervasive software have made object-oriented dynamically typed languages become increasingly popular.  ...  These languages offer dynamic software evolution by means of reflection, facilitating the development of dynamic systems. Unfortunately, this dynamism commonly imposes a runtime performance penalty.  ...  Reflection has been recognized as a suitable tool to aid the dynamic evolution of running systems, being the primary technique to obtain meta-programming, adaptiveness, and dynamic reconfiguration features  ... 
doi:10.1016/j.scico.2009.04.001 fatcat:telvn7moyfe2xanx3ojv5fr4wq
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