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Bringing Fault-Tolerant GigaHertz-Computing to Space: A Multi-Stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft
[article]
2017
arXiv
pre-print
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Miniaturized satellites, however, suffer from low reliability, as traditional hardware-based fault-tolerance (FT) concepts are ineffective for on-board computers (OBCs) utilizing modern systems-on-a-chip ...
We present the first integral, real-world solution to enable fault-tolerant general-purpose computing with modern multiprocessor-SoCs (MPSoCs) for spaceflight, thereby enabling their use in future high-priority ...
Traditional hardware-based fault-tolerance (FT) concepts for generalpurpose computing, however, are ineffective for modern, highly scaled systems-on-chip (SoCs), becoming a prime source of malfunctions ...
arXiv:1708.06931v1
fatcat:3dmd33xwhbezlc2htibwwx7yqe
An Intelligent Agent based Grid Scheduler with Enhanced Fault Tolerance
2014
International Journal of Grid and Distributed Computing
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In large-scale grid platforms, providing fault-tolerance for users is always a challenging task because of the uncertainty of network resources. ...
In this paper, we present an intelligent agent based meta-scheduler, which is aiming at improving the fault-tolerance of grid systems when running user's application. ...
Producer Agents: They are responsible for the Maintenance of core computational grid components and executing tasks/jobs on spaces and agents to support fault tolerance. ...
doi:10.14257/ijgdc.2014.7.5.03
fatcat:mc323jo6arbizonjzvmrie3o4y
Survey and future directions of fault-tolerant distributed computing on board spacecraft
2016
Advances in Space Research
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Middleware for Fault-Tolerance (AMFT). ...
In this thesis a novel cooperative task-oriented fault-tolerant distributed computing (FTDC) architecture is proposed, which caters for high performance and reliability in systems on board spacecraft. ...
Adaptive
Middleware for
Fault-Tolerant
Distributed
Computing
Chapter 7.
Novel MPSoC
based Design for
Fault-Tolerant
Distributed
Computing
Chapter 9. ...
doi:10.1016/j.asr.2016.08.017
fatcat:szoac6aiwvbs3d2dyh5smxsgqa
DeSyRe: On-demand system reliability
2013
Microprocessors and microsystems
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As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. ...
In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. ...
Transient Fault Tolerance for the SiMS RISC Processor Fault tolerance in the SiMS processor is facilitated through duplicating the instructions on-demand using a singleevent upset based fault model [20 ...
doi:10.1016/j.micpro.2013.08.008
fatcat:jg623r4hmngthk652u7qi6ibme
Architecting and Implementing Versatile Dependability
[chapter]
2005
Lecture Notes in Computer Science
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Distributed applications must often consider and select the appropriate trade-offs among three important aspects -fault-tolerance, performance and resources. ...
This renders the versatile dependability approach useful both to applications that require static fault-tolerance configurations supporting the loss/addition of resources and changing workloads, as well ...
The Architecture of our Framework Our framework is based on the Fault-Tolerant CORBA specification [2] , which has only primitive support for tunable fault-tolerance. ...
doi:10.1007/11556169_10
fatcat:wgq3pndhkng5zkljiz22jas2au
High Performance Computing Systems for Autonomous Spaceborne Missions
2001
The international journal of high performance computing applications
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high performance computing on spacecraft for deep space missions. ...
strategies for next generation spaceborne computing. ...
Advanced Computing Research. ...
doi:10.1177/109434200101500306
fatcat:wb5djaeepzdhxes32magvfq4ai
Technology Validation: NMP ST8 Dependable Multiprocessor Project II
2007
2007 IEEE Aerospace Conference
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The objective of this NMP ST8 effort is to combine high-performance, fault tolerant, COTS-based cluster processing and fault tolerant middleware in an architecture and software framework capable of supporting ...
(COTS) processors for on-board computing has become a critical need. ...
[1] 2 The project formerly was known as the Environmentally-Adaptive Fault-Tolerant Computing (EAFTC) project. integrated DM middleware suite. ...
doi:10.1109/aero.2007.352784
fatcat:q27bk5esn5gvlnppr47aeuaowm
Introduction to the Special Issue on SAMOS 2007
2008
Journal of Signal Processing Systems
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The International Symposium on Embedded Computer Systems, Architectures, Modeling and Simulation (SAMOS) is an event which annually takes place on the scenic Mediterranean island of Samos. ...
In 2007 more than 200 papers were submitted for these two events. After a very competitive selection process only about 30% of these papers have been selected for presentation. ...
The emerging field of Fault Tolerance (FT) is addressed by Borodin et al. in their paper on "Instruction-Level Fault Tolerance Configurability." ...
doi:10.1007/s11265-008-0220-8
fatcat:k7gmmhwqfvckpdalpd4nzidani
A Primer on Design Aspects and Recent Advances in Shuffle Exchange Multistage Interconnection Networks
2021
Symmetry
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This facilitates the realization of a highly efficient network design suitable for computational-intensive applications. ...
contemporary literature, this paper reviews very recent advancements in shuffle exchange multistage interconnection networks within the last few years and provides design guidelines as well as recommendations for ...
Improving Fault Tolerance Fault tolerance is regarded as a core aspect of parallel multiprocessor systems [32] . ...
doi:10.3390/sym13030378
fatcat:4bqwiubpb5anhcu7clri7eh4aq
MEAD: support for Real-Time Fault-Tolerant CORBA
2005
Concurrency and Computation
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The MEAD (Middleware for Embedded Adaptive Dependability) system attempts to identify and to reconcile the conflicts between real-time and fault tolerance, in a resource-aware manner, for distributed CORBA ...
MEAD supports transparent yet tunable fault tolerance in real-time, proactive dependability, resource-aware system adaptation to crash, communication and timing faults with bounded fault detection and ...
Via Scalable Redundancy'), the Army Research Office grant DAAD19-01-1-0646, and grant number DAAD19-02-1-0389 ('Perpetually Available and Secure Information Systems') to the Center for Computer and Communications ...
doi:10.1002/cpe.882
fatcat:mvnh3g7e4vatphkfd6tw5hf36e
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective
2008
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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The SAFES architecture is based on three main ideas: 1) reconfigurable security primitives; 2) reconfigurable hardware monitors; and 3) a hierarchy of security controllers at the primitive, system and ...
provide high-security and high-performance for a system. ...
Fig. 9 . 9 AES core architecture for the three primitives: (a) AES core without protection; (b) AES core using parity-based technique (fault detection); and (c) AES core using TMR technique (fault tolerance ...
doi:10.1109/tvlsi.2007.912030
fatcat:esroczkr4vgkvidvljaqhqcmh4
MARLA: MapReduce for Heterogeneous Clusters
2012
2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012)
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MapReduce has gradually become the framework of choice for "big data". The MapReduce model allows for efficient and swift processing of large scale data with a cluster of compute nodes. ...
We quantify the performance gains exhibited by our approach against Apache Hadoop and MARIANE in data intensive and compute intensive applications. ...
For more robust fault-tolerance, more space is required. ...
doi:10.1109/ccgrid.2012.135
dblp:conf/ccgrid/FadikaDHG12
fatcat:t6ff7z2jzfhwvciqyn4j7xjjlq
Focus beyond Quadratic Speedups for Error-Corrected Quantum Advantage
2021
PRX Quantum
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In this perspective we discuss conditions under which it would be possible for a modest fault-tolerant quantum computer to realize a runtime advantage by executing a quantum algorithm with only a small ...
We conclude that quadratic speedups will not enable quantum advantage on early generations of such fault-tolerant devices unless there is a significant improvement in how we realize quantum error correction ...
ACKNOWLEDGMENTS The authors thank Dave Bacon, Dominic Berry, Ken Brown, Eddie Farhi, Austin Fowler, Bill Huggins, Sergei Isakov, Evan Jeffrey, Cody Jones, John Platt, Rolando Somma, Nathan Wiebe, and Will Zeng for ...
doi:10.1103/prxquantum.2.010103
fatcat:fzu5v5pxuzatrfsss56a44gaie
Compiler-Directed Soft Error Mitigation for Embedded Systems
2012
IEEE Transactions on Dependable and Secure Computing
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This paper presents a compiler-based methodology for facilitating the design of fault-tolerant embedded systems. ...
Index Terms-Fault tolerance, reliability, soft error, single event upset-SEU, embedded systems design, hardware/software codesign, design space exploration. ...
Despite the wide number of different fault tolerance methods based on hardware-only and software-only, in many cases the optimal solution is an intermediate point between these two extremes. ...
doi:10.1109/tdsc.2011.54
fatcat:72lpyhcoi5eozhneoj3cth74wa
Assurance Argument Elements for Off-the-Shelf, Complex Computational Hardware
[chapter]
2020
Lecture Notes in Computer Science
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There are many aspects to the safe use of artificial intelligence. ...
To that end, we summarise issues related to the use of multi-core processors in aviation, which contextualises our problem. ...
Use of MCPs is beneficial because they provide increased computational power. It is necessary because many single-core processors are becoming obsolete. ...
doi:10.1007/978-3-030-54549-9_17
fatcat:2vpq4z6fzzaqzmp76ad7wv7l6q
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