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Adaptive 3D-IC TSV Fault Tolerance Structure Generation [article]

Song Chen, Qi Xu, Bei Yu
2018 arXiv   pre-print
In this paper, we focus on the problem of adaptive fault-tolerance structure generation.  ...  All the proposed method- ologies are embedded in a top-down TSV planning framework to form functional TSV groups and generate adaptive fault- tolerance structures.  ...  Since yield and reliability is a primary concern in 3D ICs design, a robust fault-tolerance structure is imperative.  ... 
arXiv:1803.02490v1 fatcat:w27phjdngfdwrcesirk7mxhvhy

Fault-tolerant 3D clock network

Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang
2011 Proceedings of the 48th Design Automation Conference on - DAC '11  
In this paper, we propose a novel TSV fault-tolerant unit (TFU) that can provide tolerance against TSV failures in a 3D clock network.  ...  Clock tree synthesis is one of the most important and challenging problems in 3D ICs.  ...  INTRODUCTION 3D ICs are generally considered to be one of the most promising alternatives beyond the limit of device scaling.  ... 
doi:10.1145/2024724.2024872 dblp:conf/dac/LungSHSC11 fatcat:7ks7slp5zfbrvjhrymam7m4xte

A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications

Michael OpokuAgyeman
2015 International Journal of Computer Applications  
3D NoC components than that of conventional 2D NoC.  ...  However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of  ...  [39] proposed a fault tolerant adaptive routing algorithm for homogeneous 3D NoC with 3D Bus-hybrid routers.  ... 
doi:10.5120/21541-4531 fatcat:bxyg5fnglrbwroyk7ibzyvvpem

2D Parity Product Code for TSV online fault correction and detection

Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Michael Corad Meyer, Xuan-Tu Tran
2020 REV Journal on Electronics and Communications  
Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs).  ...  Code (2D-PPC) for TSV fault-tolerance with the ability to correct one fault and detect, at least, two faults.  ...  Besides manufacturing defects, operating defects are also a considerable issue of TSV-based 3D-ICs.  ... 
doi:10.21553/rev-jec.242 fatcat:4gn67lmr4zerhacatu2qybeg6u

A thermal-aware on-line fault tolerance method for TSV lifetime reliability in 3D-NoC systems

Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
2020 IEEE Access  
Seventh, although we only demonstrate the usage of our approach on a 3D-NoC under the PARSEC benchmarks, there is no limit on the application of this work with TSVs in 3D-ICs in general.  ...  Since the temperature map of the 3D-ICs is not uniform, the fault rates are varied between the TSV groups.  ... 
doi:10.1109/access.2020.3022904 fatcat:giopjrulsjew7gzuhiyyypu5he

A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems [article]

Shashikiran Venkatesha, Ranjani Parthasarathi
2022 arXiv   pre-print
The article presents an elaborate discussion on fault models, failure mechanisms, resilient 3D routers, defect tolerance methods for the TSV based 3D NOC many-core systems.  ...  The article presents a gamut of fault tolerance solutions from logic level to processor core level in a multi-core and many-core scenario.  ...  Fault Models for TSV based 3D Network on Chips: -The conventional IC designs such as 2D IC designs have constraints which can be addressed by adopting decisive methods like 3D IC internally wire bonded  ... 
arXiv:2203.07830v1 fatcat:dsbx3o4v3femhi5d6kfrurzuoi

AFRA: A low cost high performance reliable routing for 3D mesh NoCs

S. Akbari, A. Shafiee, M. Fathy, R. Berangi
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
In this work, we address this challenge and introduce AFRA, a deadlock-free routing algorithm for 3D mesh-based NoCs that tolerates faults on vertical links.  ...  Three-dimensional network-on-chips are suitable communication fabrics for high-density 3D many-core ICs.  ...  In this work we address permanent faults on vertical TSV based links and propose AFRA, a fault tolerant routing algorithm for 3D mesh topology.  ... 
doi:10.1109/date.2012.6176490 dblp:conf/date/AkbariSFB12 fatcat:lsei5nklkjcczn5tuaakn37q2a

A Review of the Design Challenges for the 3-D on Chip Network Paradigms

Neha Jain, Mayank Patel
2017 International Journal of Computer Applications  
The next challenge in front of researchers in the domain of NoC is to use NoC architecture as the backbone of the upcoming generation of 3D chips.  ...  In this paper, we tried to exhibit and summarize the prevalent generic 3D NoC design issues highlighted by various recent research publications in the domain of NoC.  ...  Most of previous work characterizes specific TSV structures but they do not address general multi-TSV problems [7] .  ... 
doi:10.5120/ijca2017914875 fatcat:c7wzcnumq5ca3evxthiourc66m

Guest Editorial: Special Section on Emerging Trends and Computing Paradigms for Testing, Reliability and Security in Future VLSI Systems

Stefano Di Carlo, Peilin Song, Alessandro Savino
2021 IEEE Transactions on Emerging Topics in Computing  
tolerance in 3D-ICs.  ...  The paper entitled "TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology" addresses the problem of optimizing chain-type time division multiplexing access (TDMA)-based fault  ... 
doi:10.1109/tetc.2021.3070450 fatcat:afmx7blo55f3tgkizxmqn6mp2i

A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based Network-on-Chips

Hoda Naghibi Jouybari, Karim Mohammadi
2014 Microprocessors and microsystems  
In this paper, we propose FT-DyXYZ, an adaptive fault tolerant routing to tolerate permanent faulty links in 3D mesh based NOCs that uses proximity congestion information to balance traffic.  ...  These structures are so susceptible to manufacturing and runtime faults. Thus fault tolerant routing is essential to increase reliability and performance of NOC-based SOCs.  ...  Network-on-Chips (NOCs), as scalable and efficient communication structures for complex SOCs [3, 4] , together with short interconnects in 3D ICs have led to appearance of 3D NOCs for future complex and  ... 
doi:10.1016/j.micpro.2014.09.005 fatcat:32uptbsg5jgfnnemuomh5y5kcy

A non-blocking non-degrading multiple defects link testing method for 3D-Networks-on-Chip

Khanh N. Dang, Michael Conrad Meyer, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
2020 IEEE Access  
As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip.  ...  However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used.  ...  Through-Silicon-Vias (TSVs) serve as vertical wires between two adjacent layers in 3D-ICs and 3D-NoCs.  ... 
doi:10.1109/access.2020.2982836 fatcat:oj64z44bn5awrjok3cuxivtfue

2019 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 38

2019 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
SWIFT: Switch-Level Fault Simulation on GPUs. Schneider, E., +, TCAD Jan. 2019 122-135 Fault tolerance Adaptive 3D-IC TSV Fault Tolerance Structure Generation.  ...  ., +, TCAD Sept. 2019 1744-1757 Adaptive 3D-IC TSV Fault Tolerance Structure Generation. Chen, S., +, TCAD May 2019 949-960 Automatic Generation of Peak-Power Traffic for Networks-on-Chip.  ... 
doi:10.1109/tcad.2020.2964359 fatcat:qjr6i73tkrgnrkkmtjexbxberm

LDPC-Based Adaptive Multi-Error Correction for 3D Memories

Mihai Lefter, George Voicu, Thomas Marconi, Valentin Savin, Sorin Dan Cotofana
2017 2017 IEEE International Conference on Computer Design (ICCD)  
Simulation results indicate that our proposal clearly outperforms state of the art ECC schemes with fault tolerance improvements by a 4710× factor being obtained when compared to extended Hamming ECC.  ...  For evaluation purposes we consider 3D memories protected by the proposed LDPC mechanism with various data width codes implementations.  ...  This translates into fault tolerance improvements by a 4710× factor when compared to extended Hamming ECC.  ... 
doi:10.1109/iccd.2017.47 dblp:conf/iccd/LefterVMSC17 fatcat:inbxqd74vjc2jkt6g5nwzhqsiq

Topological exploration for the efficient design of three-dimensional Network on Chip architectures

Malathi Naddunoori, Devanathan. M
2020 2020 Third International Conference on Advances in Electronics, Computers and Communications (ICAECC)  
The NoC technology with shorter wires and layered structured forms the 3D Network on Chip which forms a promising and emerging field of research.  ...  With the advent of nanoscale computing the new era of communications demand IC technologies with lesser silicon footprint , low power consumption and higher bandwidths.  ...  Hypercube topology has large bandwidth with maximum fault tolerance .It is a recursive structure and has maximum fault tolerance.  ... 
doi:10.1109/icaecc50550.2020.9339506 fatcat:nv6b5k2c6jfyhdhia3xw6qkl3e

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis

Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty
2010 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
With the proposed testing cost model, designers can explore the most cost-effective integration and testing strategies for 3D IC chips. 978-1-4244-8192-7/10/$26.00 ©2010 IEEE  ...  Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller  ...  Another effective way to reduce the impact of faulty TSVs is to create TSV redundancy. A straightforward doubling redundancy of TSVs can tolerant any single TSV failure.  ... 
doi:10.1109/iccad.2010.5653753 dblp:conf/iccad/ChenNXC10 fatcat:ckme6jexcbcnxdpfiypzukxdzi
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