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Achieving Scalability in Parallel Reachability Analysis of Very Large Circuits [chapter]

Tamir Heyman, Danny Geist, Orna Grumberg, Assaf Schuster
2000 Lecture Notes in Computer Science  
This paper presents a scalable method for parallel symbolic reachability analysis on a distributed-memory environment of workstations.  ...  Our initial performance evaluation using several large circuits shows that our method can handle models that are too large to fit in the memory of a single node.  ...  Acknowledgement We would like to thank the SP Hardware Verification group in IBM Poughkeepsie and specifically John Aylward for enabling us to use their 60 nodes IBM SP system in order to perform out experiments  ... 
doi:10.1007/10722167_6 fatcat:7prbmoifkrbepibrrr53htgwky

A New Reachability Algorithm for Symmetric Multi-processor Architecture [chapter]

Debashis Sahoo, Jawahar Jain, Subramanian Iyer, David Dill
2005 Lecture Notes in Computer Science  
We identify the issues and bottlenecks in parallelizing BDD-based reachability algorithm. We show that in most cases our algorithm achieves good speedup compared to the existing sequential approaches.  ...  A naive parallelization of such algorithms is often ineffective as they have less parallelism.  ...  Any opinions, findings, and conclusions or recommendations expressed in this publication are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.  ... 
doi:10.1007/11562948_5 fatcat:vh3c5n5cwvb6to7faiduf7rvdi

Multi-threaded reachability

Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
The gains are further magnified when our threaded implementation is evaluated in the context of a parallel framework.  ...  In this paper we present a novel multi-threaded reachability algorithm that avoids this scheduling problem while increasing the latent parallelism in partitioned state space traversal.  ...  A scalable parallel reachability analysis is presented in [5] .  ... 
doi:10.1145/1065579.1065701 dblp:conf/dac/SahooJIDE05 fatcat:salapkxw65fl3ggkzx2ik4ptna

Multi-threaded reachability

D. Sahoo, J. Jain, S.K. Iyer, D.L. Dill, E.A. Emerson
2005 Proceedings. 42nd Design Automation Conference, 2005.  
The gains are further magnified when our threaded implementation is evaluated in the context of a parallel framework.  ...  In this paper we present a novel multi-threaded reachability algorithm that avoids this scheduling problem while increasing the latent parallelism in partitioned state space traversal.  ...  A scalable parallel reachability analysis is presented in [5] .  ... 
doi:10.1109/dac.2005.193854 fatcat:slh4ta7hnzalpakpfdofriigna

Scalable reachability analysis via automated dynamic netlist-based hint generation

Jiazhao Xu, Mark Williams, Hari Mony, Jason Baumgartner
2014 Formal methods in system design  
While SAT-based algorithms have largely displaced BDD-based verification techniques due to their typically higher scalability, there are classes of problems for which BDDbased reachability analysis is  ...  In this paper, we introduce a novel approach to boost the scalability of reachability computation: automated netlist-based hint generation.  ...  of the problem -or to attempt both in parallel.  ... 
doi:10.1007/s10703-014-0213-0 fatcat:py2lcmvbavarzgizkxtya3nv3a

Rekindling Parallelism

Frederic Gruau, Fabien Michel
2011 2011 Fifth IEEE Conference on Self-Adaptive and Self-Organizing Systems Workshops  
In contrast, researchers on high performance tend to narrow the scope of parallel expressiveness by preserving the sequential model of computation and defining specific language constructs that can lead  ...  We argue that parallelism will really fully blossom only when both views get unified through the achievement of a new generic computing model that, while enabling decentralized computation, also supports  ...  This shift of mindset on parallelism arises by considering it as the aggregation of basic resources available in massive quantity: An arbitrary large number of smallest as possible devices.  ... 
doi:10.1109/sasow.2011.7 dblp:conf/saso/GruauM11 fatcat:njluxdp4p5eodohxclmbw2nkhu

Parallel symbolic state-space exploration is difficult, but what is the alternative?

Gianfranco Ciardo, Yang Zhao, Xiaoqing Jin
2009 Electronic Proceedings in Theoretical Computer Science  
State-space exploration is an essential step in many modeling and analysis problems. Its goal is to find the states reachable from the initial state of a discrete-state model described.  ...  Parallel explicit state-space generation is challenging, but almost linear speedup can be achieved; however, the analysis is ultimately limited by the memory and processors available.  ...  Another relevant work is [29] , which provides another algorithm for reachability analysis in the context of CTL* model checking.  ... 
doi:10.4204/eptcs.14.1 fatcat:adcab7xyi5hgtlrrnv4fxcqiqu

Shufflecast: An Optical, Data-rate Agnostic and Low-Power Multicast Architecture for Next-Generation Compute Clusters [article]

Sushovan Das, Afsaneh Rahbar, Xinyu Crystal Wu, Zhuang Wang, Weitao Wang, Ang Chen, T. S. Eugene Ng
2021 arXiv   pre-print
An optical circuit-switched network core has the potential to overcome the inherent challenges of a conventional electrical packet-switched core of today's compute clusters.  ...  Further, we implement a complete prototype of Shufflecast in our testbed and extensively evaluate the network. Shufflecast is more power-efficient than the state-of-the-art multicast mechanisms.  ...  our reachability analysis (Section 3.3) , Figure 7 : (a) CDF of fraction of loss in reachability of Shufflecast under single relay failure.  ... 
arXiv:2104.09680v1 fatcat:j4icpko5bnhhxdkuubcri76xny

Using Decision Diagrams to Compactly Represent the State Space for Explicit Model Checking [article]

Hao Zheng, Andrew Price, Chris Myers
2020 arXiv   pre-print
The enormous number of states reachable during explicit model checking is the main bottleneck for scalability.  ...  This paper presents approaches of using decision diagrams to represent very large state space compactly and efficiently.  ...  Among all the examples, some have very large state space, and it can take enormous amount of time to find all reachable states.  ... 
arXiv:2004.14995v1 fatcat:uevupnurirgonc74hrdmlpxclu

Using decision diagrams to compactly represent the state space for explicit model checking

Hao Zheng, Andrew Price, Chris Myers
2012 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
The enormous number of states reachable during explicit model checking is the main bottleneck for scalability.  ...  This paper presents approaches of using decision diagrams to represent very large state space compactly and efficiently.  ...  Among all the examples, some have very large state space, and it can take enormous amount of time to find all reachable states.  ... 
doi:10.1109/hldvt.2012.6418238 dblp:conf/hldvt/ZhengPM12 fatcat:2kgy7nso5rf2xoqfra2guylpgu

Efficient distributed SAT and SAT-based distributed Bounded Model Checking

Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar
2006 International Journal on Software Tools for Technology Transfer (STTT)  
For the sake of scalability, at no point in the BMC computation does a single workstation have all the information.  ...  SAT-based Bounded Model Checking (BMC), though a robust and scalable verification approach, still is computationally intensive, requiring large memory and time.  ...  The work in [21] discusses techniques to parallelize the BDD-based reachability analysis.  ... 
doi:10.1007/s10009-005-0203-z fatcat:k5bapu5r4vdgfhr4gy2fa5hhra

Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking [chapter]

Malay K Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar
2003 Lecture Notes in Computer Science  
For the sake of scalability, at no point in the BMC computation does a single workstation have all the information.  ...  SAT-based Bounded Model Checking (BMC), though a robust and scalable verification approach, still is computationally intensive, requiring large memory and time.  ...  The work in [21] discusses techniques to parallelize the BDD-based reachability analysis.  ... 
doi:10.1007/978-3-540-39724-3_30 fatcat:7kfwjl2x3zhfpe6odfbtfgodzy

Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation [chapter]

Orna Grumberg, Tamir Heyman, Nili Ifergan, Assaf Schuster
2005 Lecture Notes in Computer Science  
The effectiveness of the resulting scheme is demonstrated on a number of large industrial designs as well as public benchmark circuits, all known to be hard for reachability analysis.  ...  This paper presents a novel BDD-based distributed algorithm for reachability analysis which is completely asynchronous.  ...  In order to exploit the full power of the parallel machinery and achieve scalability, it was necessary to design a new algorithm which is asynchronous in nature.  ... 
doi:10.1007/11560548_12 fatcat:enqq6rqrkfh27natwnr6mb5tva

Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies

Huy Nguyen, Michael S. Hsiao
2012 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
generation technique that is scalable to large circuits; (2) We utilize static and dynamic filters to reduce the number of potential inductive invariants that need to be proved to further reduce the computational  ...  have been achieved for many instances.  ...  In this circuit, sequential invariants were not needed to prove equivalence. A speedup of 20.11× was achieved. In b07 gray hot, we see a speedup of 53× in achieving the same result!  ... 
doi:10.1109/hldvt.2012.6418236 dblp:conf/hldvt/NguyenH12 fatcat:oxyd6vqoufc7rfnfpa5ipfrkby

A survey of recent advances in SAT-based formal verification

Mukul R. Prasad, Armin Biere, Aarti Gupta
2005 International Journal on Software Tools for Technology Transfer (STTT)  
Finally, we summarize the noteworthy achievements in this area so far, and note the major challenges in making this technology more pervasive in industrial design verification flows.  ...  Dramatic improvements in SAT solver technology over the last decade, and the growing need for more efficient and scalable verification solutions have fueled research in verification methods based on SAT  ...  Since the number of states of even small systems can be very large, e.g., a 128 bit shift register has 2 128 states, this method does not scale, in particular for sequential circuits.  ... 
doi:10.1007/s10009-004-0183-4 fatcat:d6hub3n6uzezhkl7dnneh2glgu
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