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Accurate microarchitecture-level fault modeling for studying hardware faults

Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
Since hardware faults actually manifest at a much lower level, it is unclear if such high level fault models are acceptably accurate.  ...  of faults injected under different microarchitecture-level and gate-level fault models and identify the reasons for the inability of microarchitecture-level faults to model gate-level faults in general  ...  Ting Dong for help with statistical analysis.  ... 
doi:10.1109/hpca.2009.4798242 dblp:conf/hpca/LiRKHA09 fatcat:hclbqnyecje2retgk7i5oidjxy

RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU

Athanasios Chatzidimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Maurizio Iacaruso, Mauro Pipponzi, Riccardo Mariani, Stefano Di Carlo
2017 2017 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)  
In this paper, we perform reliability assessment using statistical fault-injection on the RTL and Microarchitectural models of the same commercial ARM ® Cortex ® -A9 processor.  ...  These models, however, may not be completely accurate compared to the actual final design.  ...  Microarchitectural model For the microarchitecture-level reliability assessment, we used the GeFIN fault-injection framework [13] [14] , which is based on a state-of-the-art microarchitecture-level  ... 
doi:10.1109/dsn-w.2017.16 dblp:conf/dsn/Chatzidimitriou17 fatcat:zlnjjzwedbb7hdycisjytabamm

CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions

A. Pellegrini, R. Smolinski, L. Chen, X. Fu, S. K. S. Hari, J. Jiang, S. V. Adve, T. Austin, V. Bertacco
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
for both permanent and transient hardware faults for all but one hardware component studied.  ...  More accurate evaluations of SWAT require tests on industry strength processor, a commercial operating system, unmodified applications, and accurate low-level fault models.  ...  Furthermore, accurate modeling of hardware errors requires very detailed fault models and low-level knowledge of the design under evaluation.  ... 
doi:10.1109/date.2012.6176660 dblp:conf/date/PellegriniSCFHJAAB12 fatcat:k4ali6yqpreabmkigkvobjkcgy

Characterizing the Impact of Intermittent Hardware Faults on Programs

Layali Rashid, Karthik Pattabiraman, Sathish Gopalakrishnan
2015 IEEE Transactions on Reliability  
Index Terms-Intermittent hardware faults, fault propagation, fault diagnosis, fault injection, fault model.  ...  In this work, we characterize the impact of intermittent hardware faults in programs using faultinjection campaigns in a microarchitectural processor simulator.  ...  We thank the anonymous reviewers of the IEEE Transactions on Reliability for their help in improving this paper.  ... 
doi:10.1109/tr.2014.2363152 fatcat:xfbjctakjrhxpgina33ugjvt5a

Modeling and Analyzing the Effect of Microarchitecture Design Parameters on Microprocessor Soft Error Vulnerability

Chang Burm Cho, Wangyuan Zhang, Tao Li
2008 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computers and Telecommunication Systems  
Experimental results show that the proposed modeling techniques can accurately estimate processor reliability, runtime variation, and the performance/reliability tradeoffs in the early stages of microarchitecture  ...  High performance and reliability are essential for microprocessor design.  ...  There has been prior work on high-level reliability modeling. For example, hardware RTL models have been used in the past to estimate processor reliability [8, 16] .  ... 
doi:10.1109/mascot.2008.4770557 fatcat:kkb32g34l5davpp3x5kbopeuxa

Eliminating microarchitectural dependency from Architectural Vulnerability

Vilas Sridharan, David R. Kaeli
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
To evaluate the behavior of software in the presence of hardware faults, we must isolate the software-dependent (architecture-level masking) portion of AVF from the hardware-dependent (microarchitecture-level  ...  AVF captures both microarchitectural and architectural fault masking effects; therefore, AVF measurements cannot generate insight into the vulnerability of software independent of hardware.  ...  Faults can be masked at many levels; properly assessing the impact of each masking level is important to achieve accurate failure rate estimates.  ... 
doi:10.1109/hpca.2009.4798243 dblp:conf/hpca/SridharanK09 fatcat:jqmaxue4yfeipikmvbifrpa24u

Understanding the propagation of hard errors to software and implications for resilient system design

Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou
2008 Proceedings of the 13th international conference on Architectural support for programming languages and operating systems - ASPLOS XIII  
We achieve our goals through fault injection experiments with a microarchitecture-level full system timing simulator.  ...  We explore a cooperative hardware-software solution that watches for anomalous software behavior to indicate the presence of hardware faults.  ...  We also thank Ulya Karpuzcu for help with our simulation infrastructure.  ... 
doi:10.1145/1346281.1346315 dblp:conf/asplos/LiRSAAZ08 fatcat:t6sgrwzzlzc5ncbjkfz5clgmse

Understanding the propagation of hard errors to software and implications for resilient system design

Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou
2008 ACM SIGOPS Operating Systems Review  
We achieve our goals through fault injection experiments with a microarchitecture-level full system timing simulator.  ...  We explore a cooperative hardware-software solution that watches for anomalous software behavior to indicate the presence of hardware faults.  ...  We also thank Ulya Karpuzcu for help with our simulation infrastructure.  ... 
doi:10.1145/1353535.1346315 fatcat:ca6pbnf535a7hjpenaxuyqzr3a

Understanding the propagation of hard errors to software and implications for resilient system design

Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou
2008 SIGARCH Computer Architecture News  
We achieve our goals through fault injection experiments with a microarchitecture-level full system timing simulator.  ...  We explore a cooperative hardware-software solution that watches for anomalous software behavior to indicate the presence of hardware faults.  ...  We also thank Ulya Karpuzcu for help with our simulation infrastructure.  ... 
doi:10.1145/1353534.1346315 fatcat:pcsal3m4vfd2xkliow3ark7iva

Understanding the propagation of hard errors to software and implications for resilient system design

Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou
2008 SIGPLAN notices  
We achieve our goals through fault injection experiments with a microarchitecture-level full system timing simulator.  ...  We explore a cooperative hardware-software solution that watches for anomalous software behavior to indicate the presence of hardware faults.  ...  We also thank Ulya Karpuzcu for help with our simulation infrastructure.  ... 
doi:10.1145/1353536.1346315 fatcat:l2ipmrguofa7nmnatgraio5vau

SimpliFI: Hardware Simulation of Embedded Software Fault Attacks

Jacob Grycel, Patrick Schaumont
2021 Cryptography  
Fault injection simulation on embedded software is typically captured using a high-level fault model that expresses fault behavior in terms of programmer-observable quantities.  ...  These fault models hide the true sensitivity of the underlying processor hardware to fault injection, and they are unable to correctly capture fault effects in the programmer-invisible part of the processor  ...  accurate for hardware-level analysis. 3.  ... 
doi:10.3390/cryptography5020015 fatcat:zjo6ea5tenc43ezyro4ircilyi

Intermittent Hardware Errors Recovery: Modeling and Evaluation

Layali Rashid, Karthik Pattabiraman, Sathish Gopalakrishnan
2012 2012 Ninth International Conference on Quantitative Evaluation of Systems  
Our fault models are based on insights from related work at the physical level.  ...  To achieve this, we model a system that consists of a fault-tolerant multicore processor subject to intermittent faults.  ...  We thank the anonymous reviewers of QEST 2012 for suggestions that helped to improve this work.  ... 
doi:10.1109/qest.2012.37 dblp:conf/qest/RashidPG12 fatcat:espnueds3vfxhj5g736oo2fld4

Cross-layer system reliability assessment framework for hardware faults

A. Vallero, A. Savino, G. Politano, S. Di Carlo, A. Chatzidimitriou, S. Tselonis, M. Kaliorakis, D. Gizopoulos, M. Riera, R. Canal, A. Gonzalez, M. Kooli (+2 others)
2016 2016 IEEE International Test Conference (ITC)  
to statistically significant but slow fault injection campaigns at the microarchitecture level.  ...  different classes of hardware faults.  ...  To compute CPTs for the different structures composing a complex microprocessor we resort to microarchitecture-level fault injection, which delivers very accurate results for arraybased structures, unlike  ... 
doi:10.1109/test.2016.7805863 dblp:conf/itc/ValleroSPCCTKGR16 fatcat:gcjrnwaegbavbjd5avhw7bkaja

Characterizing fault propagation in safety-critical processor designs

Jaime Espinosa, Carles Hernandez, Jaume Abella
2015 2015 IEEE 21st International On-Line Testing Symposium (IOLTS)  
In this paper we perform fault injections in an RTL model of a processor to characterize fault propagation.  ...  The results and conclusions of this characterization will serve to devise to what extent fault injection methodologies for robustness verification using microarchitectural simulators can be employed.  ...  Figure 5 shows the percentage of faults that cause one or more errors for the 3 fault models considered in this study.  ... 
doi:10.1109/iolts.2015.7229848 dblp:conf/iolts/EspinosaHA15 fatcat:op2gf77mbvcknl3ykoet6iwlai

Using hardware vulnerability factors to enhance AVF analysis

Vilas Sridharan, David R. Kaeli
2010 SIGARCH Computer Architecture News  
Fault tolerance is now a primary design constraint for all major microprocessors.  ...  The AVF of a hardware structure is the probability that a fault in the structure will affect the output of a program.  ...  Powell for their comments on the original manuscript and the anonymous reviewers for their feedback on the final version.  ... 
doi:10.1145/1816038.1816023 fatcat:xbnptto7rbek7ggvuokewp3qky
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