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BLRL: Accurate and Efficient Warmup for Sampled Processor Simulation

L. Eeckhout
2005 Computer journal  
This paper presents the boundary line reuse latency (BLRL) which is an accurate and efficient warmup strategy.  ...  BLRL achieves a warmup that is only half the warmup for MRRL on average for the same level of accuracy.  ...  The Computer Journal Vol. 48 No. 4, 2005 BLRL: Accurate and Efficient Warmup for Sampled Processor Simulation 453 instructions under cold, warm and hot simulation.  ... 
doi:10.1093/comjnl/bxh103 fatcat:lsq65yj6cncbjdfthmc5rmol54

NSL-BLRL: Efficient CacheWarmup for Sampled Processor Simulation

L. Van Ertvelde, F. Hellebaut, L. Eeckhout, K. De Bosschere
39th Annual Simulation Symposium (ANSS'06)  
As such, we conclude that NSL-BLRL is a highly efficient and accurate cache warmup strategy for sampled processor simulation.  ...  We show using SPEC CPU2000 benchmarks that NSL-BLRL is (i) nearly as accurate as BLRL and NSL for sampled processor simulation, (ii) yields simulation time speedups of several orders of magnitude compared  ...  Acknowledgements Filip Hellebaut is supported by a grant from the Institute for the Promotion of Innovation by Science and Technology in Flanders (IWT).  ... 
doi:10.1109/anss.2006.33 dblp:conf/anss/ErtveldeHEB06 fatcat:cyk3a533t5df5l3ocsn4sgwzje