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Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses

K. Sundaresan, N.R. Mahapatra
11th International Symposium on High-Performance Computer Architecture  
In this work, we present a unified nanometer-scale bus energy dissipation and thermal model that helps designers monitor energy dissipation and temperature rise in individual wires during dynamic simulation  ...  Next, using our integrated model in a first-of-its-kind study, we study energy dissipation and thermal characteristics of instruction and data address buses with traces obtained from standard SPEC CPU2000  ...  In this work, we develop a model for activity-dependent bus line energy dissipation and temperature rise, and apply it to study address buses; however, our energy and thermal model can be used to study  ... 
doi:10.1109/hpca.2005.5 dblp:conf/hpca/SundaresanM05 fatcat:arys5jqmtbg5biwwrjlytsuneu

An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

Zhang-Ming Zhu, Bao-Tian Hao, Yun-Fei En, Yin-Tang Yang, Yue-Jin Li
2011 Chinese Physics B  
The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.  ...  On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously  ...  A simple yet accurate capacitance model is needed in order to build an accurate dynamic power model of an acceptable computational complexity.  ... 
doi:10.1088/1674-1056/20/6/068401 fatcat:zbun5rczxrga7cak36yccl4u2m

Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

Vithyalakshmi. N, Nagarajan P, Ashok Kumar.N, Vinoth. G.S
2018 International Journal of Engineering & Technology  
Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation.  ...  In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified.  ...  Introduction Scaling of low power very large scale integrated circuits has boosted the sensitivity of CMOS circuits to produce large energy dissipation.  ... 
doi:10.14419/ijet.v7i3.1.16792 fatcat:6zh6hhqk3be37etnn3endga7su

A Novel Low-Power Logic Circuit Design Scheme

Janusz A. Starzyk, Haibo He
2007 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
When the output changes its logic value, this stored energy is dissipated through the pull down path to the ground.  ...  In order to reduce this switching energy dissipation each time the load capacitor is discharged, we store its energy in the magnetic field of the inductor in the proposed SLC architecture.  ...  In this case, the stored energy will be dissipated through the pull down circuit to the ground. This energy is changed to thermal energy and needs to be removed by a cooling process.  ... 
doi:10.1109/tcsii.2006.883093 fatcat:iaye6pxefjgw5oaxhdk7vbo4ai

Review of Electromagnetic failure, optimization techniques and stress prediction in Interconnect

Arti Joshi, Rishika Sethi, Purushottam Kumawat
2014 IOSR Journal of VLSI and Signal processing  
Today, onchip global interconnect with conventional Cu/low-k and delay optimized repeater scheme faces great challenges in the nanometer regime, imposing problems of slower delay, higher power dissipation  ...  Modern electronics system integrates more complex component and devices, which result in a very complex electromagnetic field environment Moore's law has driven the scaling of digital electronic devices  ...  Devendra Kumar Somwanshi, Associate Professor, M Tech, Poornima University for their guidance and support.  ... 
doi:10.9790/4200-04222328 fatcat:s6xnhmpcjjaczjgscixmwkdmc4

Processor power estimation techniques: a survey

Hameedah Sultan, Gayathri Ananthanarayanan, Smruti R. Sarangi
2014 International Journal of High Performance Systems Architecture  
Increased power dissipation along with the resultant rise in die temperature is considered as the single largest bottleneck for increasing processor frequency and complexity.  ...  We broadly focus on estimating power using system level models, architectural simulation, hardware performance counters, on-chip temperature profiles, and program execution profiles.  ...  Lastly, for nanometer scale CMOS circuits, junction leakage is emerging as an important source of leakage power.  ... 
doi:10.1504/ijhpsa.2014.061448 fatcat:nh2vsgb2afhs5kdvcgoyyv7wsa

Microarchitecture Design [chapter]

2016 Electronic Design Automation for IC System Design, Verification, and Testing  
We also model the dependence between the throughput and power, and and uses transient analysis for thermal estimation. The thermal objectives that we consider are the peak and average temperatures.  ...  Overview of Asim Asim provides a cycle-accurate simulation framework for microprocessor perfor- Bus latency modeling As noted in Section 5.1.2, the buses (of Figure 5 .2) are modeled as ports in Asim  ... 
doi:10.1201/b19569-15 fatcat:vekug75yire5vldpb4xx6y5ooq

Thermally Aware Design

Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar
2007 Foundations and Trends® in Electronic Design Automation  
Nassif, Vidyasagar Nookala, Haifeng Qian, and Tianpei Zhang.  ...  The precise PDE that is used to model the thermal problem depends on the length scale being considered.  ...  The second and last exception is the factor max lsq ruu, which models the maximum of the latencies of the buses dec ruu and dec lsq.  ... 
doi:10.1561/1500000007 fatcat:faxvr2rvl5dsbii5afys7vw4fe

Reliability-aware and energy-efficient synthesis of NoC based MPSoCs

Yong Zou, S. Pasricha
2013 International Symposium on Quality Electronic Design (ISQED)  
However, these mechanisms to achieve fault resilience introduce power dissipation overheads that can disrupt stringent chip power budgets and thermal constraints.  ...  In this paper, we propose a novel design-time framework (RESYN) to trade-off energy consumption and reliability in the NoC fabric at the system level for MPSoCs.  ...  performance than buses [10] .  ... 
doi:10.1109/isqed.2013.6523678 dblp:conf/isqed/ZouP13 fatcat:bgq6c7nynbaolj6lvqm7yu23du

NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults

Sudeep Pasricha, Yong Zou
2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)  
In this paper, we propose a novel fault tolerant routing scheme (NS-FTR) for NoC architectures that combines the North-last and South-last turn models to create a robust hybrid NoC routing scheme.  ...  The proposed scheme is shown to have a low implementation overhead and adapt to design time and runtime faults better than existing turn model, stochastic random walk, and dual virtual channel based routing  ...  NL and SL Turn Models The north last (NL) turn model for deadlock-free routing was first introduced by Glass et al. [26] for large scale off-chip 2D mesh networks.  ... 
doi:10.1109/aspdac.2011.5722231 dblp:conf/aspdac/PasrichaZ11 fatcat:ikz6l456o5awhma56krl2uzgii

Science and Engineering Beyond Moore's Law

R. K. Cavin, P. Lugli, V. V. Zhirnov
2012 Proceedings of the IEEE  
., to improve the performance and reduce switching energy for devices whose smallest features are on the order of a few nanometers.  ...  curve for cost reductions that have historically been achieved via Moore's Law scaling.  ...  Scaling to nanometer dimensions poses several problems connected, e.g., to fluctuations, friction, and dissipation mechanisms at the nanoscale.  ... 
doi:10.1109/jproc.2012.2190155 fatcat:djic4ujcnbgd7jaecu7ibpqd6e

Desigining Circuits from Imperfect Components in VISI Giga-scale Technologies

Antonio RUBIO, Ferran MARTORELL, Francesc MOLL
2006 International Journal of the Society of Materials Engineering for Resources  
In the paper techniques for the design of robust electronic systems in spite of the low quality of components are presented for the two scenarios.  ...  With this principle and by using a quality control at the end of the production line (Test Technology) the semiconductor industry has reached very high productivity levels.  ...  The maximum dissipated energy density cannot overcome the limit for the materials that build the devices (100 W/cm2 for silicon [18, 19] ).  ... 
doi:10.5188/ijsmer.14.1 fatcat:gauadohsdrfjpgz2k57zs5x2lu

Reaching the limits of low power design

J. S. Hobbs, T. W. Williams
2008 2008 Asia and South Pacific Design Automation Conference  
And how do we handle verification of these complex implementations? This paper explores possible methods for improving the "power capacity" of power sensitive designs.  ...  As process technologies continue to shrink, and feature demands continue to increase, more and more capabilities are being pushed into smaller and smaller packages.  ...  Low Power IP Connectivity intellectual property (IP) for high-speed serial buses such as USB 2.0, PCI Express, and HDMI was not architected with power in mind.  ... 
doi:10.1109/aspdac.2008.4484048 dblp:conf/aspdac/HobbsW08 fatcat:mtft7h2afbe2lcaicjlvi5jgbi

An Outlook on Design Technologies for Future Integrated Systems

G. De Micheli
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper surveys design requirements and solutions for heterogeneous systems and addresses design technologies for realizing them.  ...  The economic and social demand for ubiquitous and multifaceted electronic systems-in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies-is  ...  Asynchronous models are more accurate: Despite the fact that exact timing information is not used, asynchronous models assume different timing for different transitions, or equivalently that at each "equivalent  ... 
doi:10.1109/tcad.2009.2021008 fatcat:2qujxzmnjbfebd4fg3bnrzsjua

A practical guide for building superconducting quantum devices [article]

Yvonne Y. Gao, M. Adriaan Rol, Steven Touzard, Chen Wang
2021 arXiv   pre-print
More importantly, we aim to provide a synoptic outline of the core techniques that underlie most cQED experiments and offer a practical guide for a novice experimentalist to design, construct, and characterize  ...  electrodynamics (cQED) technology, which has emerged as one of the most promising physical systems that is capable of addressing the key challenges in realizing full-stack quantum computing on a large scale  ...  Acknowledgement 38 ACKNOWLEDGEMENT We thank Luigi Frunzio, Shyam Shankar, and Leo DiCarlo for their insightful feedback on the manuscript. We thank E. Dogan and S.  ... 
arXiv:2106.06173v2 fatcat:r7n7tmblcjfwzlghqfe3i72spi
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