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Accelerating two-dimensional page walks for virtualized systems
2008
ACM SIGOPS Operating Systems Review
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Nested paging complements existing page walk hardware to form a two-dimensional (2D) page walk, which reduces the need for hypervisor intervention in guest page table management. ...
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. ...
Acknowledgments The authors acknowledge the following individuals for their technical contribution to the definition and implementation of nested paging in AMD processors: Kevin McGrath, Mike Clark, Alex ...
doi:10.1145/1353535.1346286
fatcat:djw26rrhffao7fav2as7j4zkbq
Accelerating two-dimensional page walks for virtualized systems
2008
SIGARCH Computer Architecture News
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Nested paging complements existing page walk hardware to form a two-dimensional (2D) page walk, which reduces the need for hypervisor intervention in guest page table management. ...
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. ...
Acknowledgments The authors acknowledge the following individuals for their technical contribution to the definition and implementation of nested paging in AMD processors: Kevin McGrath, Mike Clark, Alex ...
doi:10.1145/1353534.1346286
fatcat:5qt2ltndsvhetdtwauzw5zau6y
Accelerating two-dimensional page walks for virtualized systems
2008
SIGPLAN notices
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Nested paging complements existing page walk hardware to form a two-dimensional (2D) page walk, which reduces the need for hypervisor intervention in guest page table management. ...
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. ...
Acknowledgments The authors acknowledge the following individuals for their technical contribution to the definition and implementation of nested paging in AMD processors: Kevin McGrath, Mike Clark, Alex ...
doi:10.1145/1353536.1346286
fatcat:576w3qetwfbhhl4rjt74tpvsey
Accelerating two-dimensional page walks for virtualized systems
2008
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems - ASPLOS XIII
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Nested paging complements existing page walk hardware to form a two-dimensional (2D) page walk, which reduces the need for hypervisor intervention in guest page table management. ...
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. ...
Acknowledgments The authors acknowledge the following individuals for their technical contribution to the definition and implementation of nested paging in AMD processors: Kevin McGrath, Mike Clark, Alex ...
doi:10.1145/1346281.1346286
dblp:conf/asplos/BhargavaSSM08
fatcat:3arntzy7q5avtkbkxdnled6llu
Supporting Address Translation for Accelerator-Centric Architectures
2017
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
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Second, to compensate for the effects of the widely used data tiling techniques, we design a shared level-two TLB to serve private TLB misses on common virtual pages, eliminating duplicate page walks from ...
This two-level TLB design effectively reduces page walks by 75.8% on average. ...
ACKNOWLEDGMENT We thank the anonymous reviewers for their feedback. ...
doi:10.1109/hpca.2017.19
dblp:conf/hpca/HaoFRC17
fatcat:cqywaosz3rddnkm4aiehc674cu
Evaluating the impacts of hugepage on virtual machines
2016
Science China Information Sciences
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We apply ABH to different paging modes in virtualized systems. ...
This pressure is more prominent in a virtualized system, which adds an additional layer of address translation. Page walks due to TLB misses can result in a significant performance overhead. ...
The two-dimensional page walk needs more memory accesses to complete an address mapping, which yields much higher penalty than page walk in a native system [3] . ...
doi:10.1007/s11432-015-0764-7
fatcat:qkqb3gzjjrb33ng7irgle43cny
Large pages and lightweight memory management in virtualized environments
2015
Proceedings of the 48th International Symposium on Microarchitecture - MICRO-48
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In response, virtualization software often (though it doesn't have to) splinters guest operating system (OS) large pages into small system physical pages, sacrificing address translation performance for ...
For example, they reduce opportunities to deduplicate memory among virtual machines in overcommitted systems, interfere with lightweight memory monitoring, and hamper the agility of virtual machine (VM ...
ACKNOWLEDGMENTS We thank Jim Mattson for his help and valuable feedback. We thank Kathryn McKinley and Mark Hill for their insights and feedback in preparing the final version of the paper. ...
doi:10.1145/2830772.2830773
dblp:conf/micro/PhamVLB15
fatcat:5bcglr5xyvhcfm4y2vk3l7fahe
NeuMMU: Architectural Support for Efficient Address Translations in Neural Processing Units
[article]
2019
arXiv
pre-print
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This paper makes a case for enabling address translation in NPUs to decouple the virtual and physical memory address space. ...
To satisfy the compute and memory demands of deep neural networks, neural processing units (NPUs) are widely being utilized for accelerating deep learning algorithms. ...
Under x86-64 based translation system, the paged virtual memory is implemented using a radix tree for their page-tables. ...
arXiv:1911.06859v1
fatcat:pyzkc6lh55gslf3kzzgseddt5q
Translation caching
2010
Proceedings of the 37th annual international symposium on Computer architecture - ISCA '10
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In particular, these caches accelerate the page table walk that occurs after a miss in the Translation Lookaside Buffer. ...
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page table. ...
A NTLB hit allows the two-dimensional page walk to skip the entire page walk on the virtual machine monitor's page table for a single guest page table access, but not the accesses to the upper levels of ...
doi:10.1145/1815961.1815970
dblp:conf/isca/BarrCR10
fatcat:d7f55aa4nbbd5konroxosutd6e
Quantifying and Modeling Coordination and Coherence in Pedestrian Groups
2017
Frontiers in Psychology
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When compared to reshuffled virtual control groups, the results indicate lower-dimensional behavior and a stronger, more stable coupling of walking speed in real groups. ...
They also offer a methodological approach for investigating group dynamics in more complex settings. ...
The authors would also like to thank Henry Harrison for his help with subject recruitment. ...
doi:10.3389/fpsyg.2017.00949
pmid:28701966
pmcid:PMC5488766
fatcat:kasuroqmirgflfhhsg7rcxh37i
An Immersive Virtual Environment for Special Relativity
2000
International Conference in Central Europe on Computer Graphics and Visualization
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The implementation supports multiprocessor and multipipe systems for fast rendering and the same frame rates can be achieved for relativistic visualization as for non-relativistic rendering. ...
The relativistic-vehicle-control metaphor-a physically based camera control technique-is introduced for navigating at high velocities. Acceleration of the relativistic observer is investigated. ...
Special thanks to Michael Doggett, Stefan Gumhold, Bettina Salzer, and Nikolaus Weiskopf for their help in preparing this paper. ...
dblp:conf/wscg/Weiskopf00
fatcat:7srie6wcgbb2vpd6xkb2rvuoyi
Near-Memory Address Translation
2017
2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)
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These systems implement a two-dimensional virtual address space where each of the segments is then split into pages. ...
For example, a page walk to two consecutive pages in the virtual address space will likely share the same three entries of the upper levels (i.e., PML4, PDP, and PD). ...
Hence, achieving the performance of an ideal MMU with zero overhead for page walks. ...
doi:10.1109/pact.2017.56
dblp:conf/IEEEpact/PicorelJF17
fatcat:zgsfj7v4pjazdcfb5hcyemndea
Hardware Translation Coherence for Virtualized Systems
[article]
2017
arXiv
pre-print
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To improve system performance, modern operating systems (OSes) often undertake activities that require modification of virtual-to-physical page translation mappings. ...
We perform detailed studies using KVM-based virtualization, showing that HATRIC achieves up to 30% performance and 10% energy benefits, for per-CPU area overheads of 2%. ...
We believe, therefore, that HATRIC will become essential for upcoming systems, especially as they rely on page migration to exploit heterogeneous memory systems. ...
arXiv:1701.07517v2
fatcat:f4gwxcie2ndyvceimhfal3ybce
Minimal-overhead virtualization of a large scale supercomputer
2011
Proceedings of the 7th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments - VEE '11
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We describe three techniques essential for achieving such low overhead: passthrough I/O, workload-sensitive selection of paging mechanisms, and carefully controlled preemption. ...
Virtualization has the potential to dramatically increase the usability and reliability of high performance computing (HPC) systems. ...
We believe our results represent the largest scale study of HPC virtualization by at least two orders of magnitude, and we have described how such performance is possible. ...
doi:10.1145/1952682.1952705
dblp:conf/vee/LangePDBBSM11
fatcat:jkhsx56ybnbhbbinribfbgy3k4
Minimal-overhead virtualization of a large scale supercomputer
2011
SIGPLAN notices
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We describe three techniques essential for achieving such low overhead: passthrough I/O, workload-sensitive selection of paging mechanisms, and carefully controlled preemption. ...
Virtualization has the potential to dramatically increase the usability and reliability of high performance computing (HPC) systems. ...
We believe our results represent the largest scale study of HPC virtualization by at least two orders of magnitude, and we have described how such performance is possible. ...
doi:10.1145/2007477.1952705
fatcat:ibanfnupyrc7xj3bzj5c46cbpu
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