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Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture based on FPGAs

Sarah Pilz, Florian Porrmann, Martin Kaiser, Jens Hagemeyer, James M. Hogan, Ulrich Rückert
2020 Algorithms  
In this work, we present a scalable FPGA-based system architecture to accelerate the comparison of binary strings.  ...  This paper is concerned with Field Programmable Gate Arrays (FPGA)-based systems for energy-efficient high-throughput string comparison.  ...  Discussion and Future Work A scalable streaming-based system architecture for high-throughput bit string comparisons on FPGAs has been presented.  ... 
doi:10.3390/a13020047 fatcat:bl4g3mnwe5d5tjtu34kmreiciu

A Study on Speeding up Spark with Big Data Compression through Xeon/FPGA in VMware Virtualization Communication Model

R.Prem Kumar
2017 International Journal for Research in Applied Science and Engineering Technology  
We propose a novel scalable Apache Spark with Xeon/FPGA data compression approach in VMware virtualization communication model.  ...  Based on specific on-Cloud data compression requirements, In addition to different compression technologies and methodologies, selection of a good data compression tool is most important.  ...  DATA COMPRESION USING APACHE SPARK THROUGH XEON/FPGA Spark is a top-level project of the Apache Software Foundation, designed to be used with a range of programming languages and on a variety of architectures  ... 
doi:10.22214/ijraset.2017.9236 fatcat:2hx3pq3kmvfhzccgoe7i43y7me

Parallel String Matching Problems with Computing Models An Analysis of the Most Recent Studies

K ButchiRaju, Chinta Someswara Rao, S. Viswanadha Raju
2013 International Journal of Computer Applications  
We survey the current techniques to handle with the problem of parallel string matching with computing models.  ...  We focus on current developments of parallel string matching, computing models, and the central ideas of the algorithms and their complexities.  ...  It also present a scalable, high-throughput, Memory-efficient Architecture for large-scale String Matching (MASM) based on a pipelined binary search tree.  ... 
doi:10.5120/13321-0738 fatcat:ca3hjbzpxrc2rgjn7tjmhca4ni

Scalable Automaton Matching for High-Speed Deep Content Inspection

Ying-Dar Lin, Kuo-Kun Tseng, Chen-Chou Hung, Yuan-Cheng Lai
2007 21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07)  
This paper presents a scalable automaton matching (SAM) design, which uses Aho-Corasick (AC) algorithm with two parallel acceleration techniques, root-indexing and pre-hashing.  ...  String matching plays a central role in content inspection applications such as intrusion detection, anti-virus, anti-spam and Web filtering.  ...  In this paper, we propose a scalable automaton matching (SAM) which is based on the Aho-Corasick (AC) algorithm with external memory architecture.  ... 
doi:10.1109/ainaw.2007.318 dblp:conf/aina/LinTHL07 fatcat:onwgoduaj5ajlh4u2mddf23acu

Accelerating Population Count with a Hardware Co-Processor for MicroBlaze

Iouliia Skliarova
2021 Journal of Low Power Electronics and Applications  
The entire system was implemented and tested on a Nexys-4 prototyping board containing a low-cost/low-power Artix-7 FPGA.  ...  This paper proposes a Field-Programmable Gate Array (FPGA)-based hardware accelerator for assisting the embedded MicroBlaze soft-core processor in calculating population count.  ...  In [30] a generic system architecture is proposed for binary string comparisons that is based on a Virtex Ul-traScale+ FPGA.  ... 
doi:10.3390/jlpea11020020 doaj:e88974e618724e8a9a654d819daffdcb fatcat:erh3ystnxrbbde5lhyzduk2ob4

VHDL IMPLEMENTATION OF GENETIC ALGORITHM FOR 2-BIT ADDER

VEDAVATHI. A, MEENA. K.V, GAYATRI MALHOTRA
2014 International Journal of Electronics and Electical Engineering  
The paper discusses on Cartesian Genetic Programming for evolving gate level designs and proposes Evolvable unit for 2-bit adder based on Genetic Algorithm.  ...  Future planetary and deep space exploration demands that the space vehicles should have robust system architectures and be reconfigurable in unpredictable environment.  ...  Fig. 2 FPGA-Based Runtime Configuration System Architecture The reconfigurable hardware is used as the target to evolve. It executes the desired functionalities.  ... 
doi:10.47893/ijeee.2014.1120 fatcat:6hl3j7axdvaozmahmtz7wbfoki

Non-Relational Databases on FPGAs: Survey, Design Decisions, Challenges [article]

Jonas Dann, Daniel Ritter, Holger Fröning
2020 arXiv   pre-print
To facilitate understanding of this emerging domain, we explore the fit of FPGA acceleration for NRDS with a focus on data model variety.  ...  system with FPGAs.  ...  The architecture is based on a set of nodes in a networked environment, forming a cluster.  ... 
arXiv:2007.07595v1 fatcat:eganwap76ffpzbl6fztprecawq

A High Throughput String Matching Architecture for Intrusion Detection and Prevention

Lin Tan, Timothy Sherwood
2005 SIGARCH Computer Architecture News  
Through the careful co-design and optimization of our our architecture with a new string matching algorithm we show that it is possible to build a system that is 10 times more efficient than the currently  ...  detection system is a string matching algorithm.  ...  Table 3 : 3 Detailed Comparison of Our Bit Split FSM Design and FPGA-based Designs. g = group size. 1B/cc = read in one byte per cycle time.  ... 
doi:10.1145/1080695.1069981 fatcat:rm5elxgblncxdb2p2jvl3e562u

Deep network packet filter design for reconfigurable devices

Young H. Cho, William H. Mangione-Smith
2008 ACM Transactions on Embedded Computing Systems  
For instance, one of the most widely used network intrusion detection systems, Snort, configured with 845 patterns, running on a dual 1-GHz Pentium III system, can sustain a throughput of only 50 Mbps.  ...  We designed scalable deep packet filters on field programmable gate arrays (FPGAs) to search for all data independent patterns simultaneously.  ...  Output from the 1-bit register controls the subsequent 1-bit comparison result. The content of the register A, B, and C represent the string stream 'PATTERNS.'  ... 
doi:10.1145/1331331.1331345 fatcat:qnqk4vsa6ffxncryxt57fkg34i

Heterogeneous Cloud Framework for Big Data Genome Sequencing

Chao Wang, Xi Li, Peng Chen, Aili Wang, Xuehai Zhou, Hong Yu
2015 IEEE/ACM Transactions on Computational Biology & Bioinformatics  
In this paper, we propose a novel FPGA-based acceleration solution with MapReduce framework on multiple hardware accelerators.  ...  Also, as a practical study, we have built a hardware prototype on the real Xilinx FPGA chip.  ...  Since the KMP algorithm is designed to match the input stream against a single string, one matching unit is required per string, and the hardware system is composed of a linear array of matching units.  ... 
doi:10.1109/tcbb.2014.2351800 pmid:26357087 fatcat:52gw5e6o6jc5tefrr3xau3kdcm

A 1 cycle-per-byte XML parsing accelerator

Zefu Dai, Nick Ni, Jianwen Zhu
2010 Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10  
In this paper, we detail the design of the first complete field programmable gate array (FPGA) accelerator capable of XML well-formed checking, schema validation, and tree construction at a throughput  ...  This is a significant advancement from 40 CPB, the best previous reported commercial result. We demonstrate our design on a Xilinx Virtex-5 board, which successfully saturates a 1 Gbps Ethernet link.  ...  In addition, we examine the implementation cost and speed on FPGA, and scalability issues.  ... 
doi:10.1145/1723112.1723148 dblp:conf/fpga/DaiNZ10 fatcat:f4kgjzc4bvd3vjspjbhmbb67bi

A Survey on the Application of FPGAs for Network Infrastructure Security

Hao Chen, Yu Chen, Douglas H. Summerville
2011 IEEE Communications Surveys and Tutorials  
This paper presents a survey of the state-of-art in FPGA-based implementations that have been used in the network infrastructure security area, categorizing currently existing diverse implementations.  ...  FPGAs support the performance demands of security operations as well as enable architectural and algorithm innovations in the future.  ...  The result shows that the FPGA-based string matcher exceeds the performance of the software-based system by a factor of 600 for large patterns.  ... 
doi:10.1109/surv.2011.072210.00075 fatcat:4yew6yqt25expelxenskh22b4m

A platform-based SoC design and implementation of scalable automaton matching for deep packet inspection

Ying-Dar Lin, Kuo-Kun Tseng, Tsern-Huei Lee, Yi-Neng Lin, Chen-Chou Hung, Yuan-Cheng Lai
2007 Journal of systems architecture  
This paper presents a scalable automaton matching (SAM) coprocessor that uses Aho-Corasick (AC) algorithm with two parallel acceleration techniques, root-indexing and pre-hashing.  ...  In the platform-based SoC implementation of the Xilinx ML310 FPGA, the proposed hardware architecture can achieve almost 10.7 Gbps and support over 10,000 patterns for virus, which is the largest pattern  ...  In our evaluation, we implemented SAM on a System On Chip (SoC) based platform with Xilinx FPGA Virtex2P and EDK design tool. The rest of this paper is organized as follows.  ... 
doi:10.1016/j.sysarc.2007.03.005 fatcat:dynnljjwcnerbl23ppzufz5r2e

A MEMORY EFFICIENT HARDWARE BASED PATTERN MATCHING AND PROTEIN ALIGNMENT SCHEMES FOR HIGHLY COMPLEX DATABASES

M.Anto Bennet, S. Sankaranarayanan, M. Deepika, N. Nanthini, S. Bhuvaneshwari, M. Priyanka
2017 International Journal on Smart Sensing and Intelligent Systems  
In the proposed system, the above methodology has been extended to implement a memory efficient FPGA-hardware based Network Intrusion Detection System (NIDS) to speed up network processing.  ...  A Finite State Machine (FSM) based Processing Elements (PE) unit to achieve minimum number of states for pattern matching and bit wise early intrusion detection to increase the throughput by pipelining  ...  A scalable, highthroughput, Memory-efficient Architecture for large-scale String Matching (MASM) based on a pipelined Binary Search Tree (BST) was presented.  ... 
doi:10.21307/ijssis-2017-239 fatcat:z4mjfj5ni5fg3nomftcwqqzo3y

Reconfigurable Hardware Accelerators: Opportunities, Trends, and Challenges [article]

Chao Wang, Wenqi Lou, Lei Gong, Lihui Jin, Luchao Tan, Yahui Hu, Xi Li, Xuehai Zhou
2017 arXiv   pre-print
Nowadays, in top-tier conferences of computer architecture, emerging a batch of accelerating works based on FPGA or other reconfigurable architectures.  ...  Among the typical heterogeneous architectures above, FPGA-based reconfigurable accelerators have two merits as follows: First, FPGA architecture contains a large number of reconfigurable circuits, which  ...  ForeGraph [100] implements a large-scale graph processing accelerator based on a multi-FPGA architecture.  ... 
arXiv:1712.04771v1 fatcat:3lxv45qb4zaqpagtn3eghrmroe
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