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ReConfigME: a detailed implementation of an operating system for reconfigurable computing
2006
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
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But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. ...
If the sequence of application loading and unloading is not known in advance, all resource allocation cannot be performed at design time because the availability of resources changes dynamically. ...
They would also like to acknowledge contributions from both Martyn George and Maria Dahlquist. ...
doi:10.1109/ipdps.2006.1639475
dblp:conf/ipps/WigleyKJ06
fatcat:6ucsxf4zpnfwvl7mqiqoc4ot4m
Build Automation and Runtime Abstraction for Partial Reconfiguration on Xilinx Zynq UltraScale+
2020
2020 International Conference on Field-Programmable Technology (ICFPT)
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Partial reconfiguration (PR) is fundamental to building adaptive systems on modern FPGA SoCs, where hardware can be adapted dynamically at runtime. ...
Our tools provides automation and abstraction layers, from defining PR configurations through to compiling and packaging Linux with support for userspace PR control, targeted for nonexperts. ...
ACKNOWLEDGEMENT This work was supported by the UK Engineering and Physical Sciences Research Council, grant EP/N509796/1. ...
doi:10.1109/icfpt51103.2020.00037
fatcat:jpzzd3wfhfbazpcmp4ub46yt5u
D4.1 Programming Language And Runtime System: Requirements
2016
Zenodo
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This document elaborates the requirements for the VINEYARD programming model and runtime system. ...
The VINEYARD projects aims to achieve easy-to-use and transparent acceleration of data analytics. ...
Infiniband network is used to connect MPC-X with the CPUs. All DFEs can be allocated dynamically. ...
doi:10.5281/zenodo.898162
fatcat:h4qoibk26vfzdao5badtj6fdie
FOS: A Modular FPGA Operating System for Dynamic Workloads
[article]
2020
arXiv
pre-print
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Further, to dynamically maximise the utilisation transparently from the users, FOS employs resource-elastic scheduling to arbitrate the FPGA resources in both time and spatial domain for any type of accelerators ...
However, current FPGA systems fail to achieve modularity and support for multi-tenancy due to dependencies between system components and lack of standardised abstraction layers. ...
However, this alone does not enable the flexible resource allocation required for the maximum utilisation of the resources. ...
arXiv:2001.09990v1
fatcat:z27xr3hkmvcdtd7aouyu3ymxfu
SoK: On the Security Challenges and Risks of Multi-Tenant FPGAs in the Cloud
[article]
2020
arXiv
pre-print
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This is enabled by leveraging the partial reconfiguration property of FPGAs, which allows to split the FPGA fabric into several logically isolated regions and reconfigure the functionality of each region ...
We conclude with our insights and a call for future research to tackle these challenges. ...
The next question of FPGA virtualization concerns the level of granularity of FPGA primitives that would get abstracted into a resource pool available for tenants to consume. ...
arXiv:2009.13914v2
fatcat:mbdpjfuoljderjhopoppxkxkoe
Project Beehive: A Hardware/Software Co-designed Stack for Runtime and Architectural Research
[article]
2017
arXiv
pre-print
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The objective of Project Beehive is to provide a modern platform for experimentation on emerging applications, programming languages, compilers, runtimes, and low-power heterogeneous many-core architectures ...
To that end, we present Project Beehive: A Hardware/Software co-designed stack for runtime and architectural research. ...
manager which can be used to discover IP on the programmable logic and allocate it a speci c process thread. e so ware library also provides a simple interface with IP blocks between the virtual memory ...
arXiv:1509.04085v3
fatcat:2w4mj27u5zeqzkbcktg3cjwfeu
FPGA Dynamic and Partial Reconfiguration
2018
ACM Computing Surveys
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Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). ...
We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. ...
Here the FPGA implements a soft processor (such as a MIPS processor) and a number of IP cores. The IP cores are controlled by the software running on the soft processor. ...
doi:10.1145/3193827
fatcat:tbks3e734zdkdceihncpdeawia
NFV Platform Design: A Survey
[article]
2020
arXiv
pre-print
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use cases. ...
Then we thoroughly explore the design space and elaborate the implementation choices each platform opts for. ...
Priyanka Naik for her valuable feedback. ...
arXiv:2002.11059v2
fatcat:zgafnd6xmvdzngkukq6qicf3gu
Virtual Machine for Software Defined Radio: Evaluating the Software VM Approach
2010
2010 10th IEEE International Conference on Computer and Information Technology
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We study the impact of using a virtual machine for the configuration of radio physical layer protocols on a real hardware platform: the Magali chip. ...
The results, obtained using the mixed SystemC/VHDL cycle accurate simulator of the Magali platform, show that, although the proof of concept is valid and functional, extra optimizations, such as additionnal ...
Once the bytecode is downloaded to the target RVM several runtime steps still need to be done. • Allocation and resource sharing can and should be associated with the virtual machine to increase the portability ...
doi:10.1109/cit.2010.334
dblp:conf/IEEEcit/AbdallahRFM10
fatcat:fpesfkwskvgtveiqu3ftdy34s4
FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators
2011
2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
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In this paper, we present FUSE, a framework for HW accelerator abstraction that provides: 1) transparency to the SW designer at the application level; and 2) OS support for easy HW accelerator integration ...
SoCs can be implemented on a single FPGA, offering designers a unique opportunity for Embedded Systems. ...
Katherine Compton and Dr. Mehrdad Moallem for their advice. ...
doi:10.1109/fccm.2011.48
dblp:conf/fccm/IsmailS11
fatcat:fcxcxdceibg3vb4qmu4i5opfaa
Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach
2017
2017 Euromicro Conference on Digital System Design (DSD)
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Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. ...
, heterogeneous co-processors and using advanced hardware integration technologies with the novel UNIMEM Global Address Space memory system. ...
The work presented in this paper reflects only authors' view and the European Commission is not responsible for any use that may be made of the information it contains. ...
doi:10.1109/dsd.2017.37
dblp:conf/dsd/RigoPPRDMDBMMBL17
fatcat:jumekx7n6vcmvnu32epz3tp6py
Microkernel hypervisor for a hybrid ARM-FPGA platform
2013
2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors
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It supports discrete hardware accelerators, dynamically reconfigurable regions, and regions of virtual fabric, allowing for application isolation and simpler use of hardware resources. ...
We propose virtualized execution and management of software and hardware tasks using a microkernel-based hypervisor running on a commercial hybrid computing platform (the Xilinx Zynq). ...
However, DPR allows for highly customised IP cores for better performance.
IV. ...
doi:10.1109/asap.2013.6567578
dblp:conf/asap/PhamJCFM13
fatcat:splm2qik7repjlioeuqz6dyoxe
CAP-VMs: Capability-Based Isolation and Sharing for Microservices
[article]
2022
arXiv
pre-print
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Using these two primitives, we build more expressive mechanisms for efficient cross-cVM communication. ...
We describe cVMs, a new VM-like abstraction that uses memory capabilities to isolate application components while supporting efficient data sharing, all without mandating application code to be capability-aware ...
2× and an order of magnitude speedup for the single-core FPGA platform depending on the mechanism and buffer size. ...
arXiv:2202.05732v1
fatcat:cwxrqi7ma5bb5eokwpcpscz4vy
The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres
[chapter]
2016
Lecture Notes in Computer Science
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VINEYARD will foster the expansion of the soft-IP core industry, currently limited in the embedded systems, to the data-centre market. ...
VINEYARD aims to develop an integrated platform for energy-e cient data centres based on new servers with novel, coarse-grain and fine-grain, programmable hardware accelerators. ...
Acknowledgment This project has received funding from the European Unions Horizon 2020 research and innovation programme under grant agreement No 687628. ...
doi:10.1007/978-3-319-30481-6_1
fatcat:4yvigra2w5aa7dakazch6x3qni
BITMAN: A tool and API for FPGA bitstream manipulations
2017
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
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The functionality includes high-level commands such as cutting out regions of a bitstream and placing or relocating modules on an FPGA as well as low-level commands for modifying primitives and for routing ...
BIT-MAN supports recent Xilinx FPGAs that can be used by the ISE and Vivado tool suites of the FPGA vendor Xilinx, including latest Virtex-6, 7 Series, UltraScale and UltraScale+ series FPGAs. ...
High performance reconfigurable systems, such as proposed in the projects EXTRA [2] , ECOSCALE [3] , or OpenStackenabled virtualized FPGA platform [4] require run-time allocation of hardware accelerators ...
doi:10.23919/date.2017.7927114
dblp:conf/date/PhamHK17
fatcat:e6fpjzcsi5b6lab6ckvyklzkem
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