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ATPG for timing-induced functional errors on trigger events in hardware-software systems

S. Arekapudi, Fei Xin, Jinzheng Peng, I.G. Harris
Proceedings The Seventh IEEE European Test Workshop  
Y datain write full empty read dataout out in ¢ 4 × ( ã ¢ å h Ö 0 Ù u â í ß ì h Ö 0 ß C Ý d Ù ç ç Ù } ç ! Ý d ß t Ô Ô å h Û h × Ý Õ 3 Þ × ( Û h ã ê c × ( Õ Õ u ¢ u & ¢ u v 2.1.  ...  Timing Fault Model â × ( Ô × x Û ¤ ã p ä 2 Õ ¢ å h ae x Þ 0 ç Ù d è C × ç # Þ H ç × u ä ' Þ é ¤ Ù ç × ( ã ¢ Û ¤ Õ ¢ ae ( ç Õ 3 Ö 0 Ù Õ ¢ ç 0 ç X × ( ã ¢ Û h Ù Ú ê Õ 3 ae x ë å h Ù ç g Õ Þ × ( Û ¤ Ý ß ¢  ...  Harris, "Test Pattern Generation for Timing-Induced Functional Errors in Hardware-Software Systems," [5] Q. Zhang and I.  ... 
doi:10.1109/etw.2002.1029635 dblp:conf/ets/ArekapudiXPH02 fatcat:5tems66c3zhnbdwxygjuseevmy

Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262

Ahmet Cagri Bagbaba, Felipe Augusto Da Silva, Christian Sauer
2018 Zenodo  
Higher Tool Confidence Level (TCL) is needed for tools used on the verification of safety-critical SoCs, aiming to achieve the required Automotive Safety Integrity Level in ISO 26262.  ...  To do this, we compare the fault-list generated by the fault injection (FI) simulator with the Automatic Test Pattern Generation (ATPG) flow for stuck-at (SA) fault types.  ...  The former defines checkers which monitor the systems and trigger error response and recovery features when necessary.  ... 
doi:10.5281/zenodo.3361606 fatcat:4qmao4fpojesvkxvq46woqmnwa

On the validation of embedded systems through functional ATPG

Giuseppe Di Guglielmo
2008 2008 Ph.D. Research in Microelectronics and Electronics  
In fact, synthesis tools are large software systems history shows to be prone to error.  ...  O, in order to model asynchronous EEFSM composition (Section 5.7), where none, one or more EEFSMs may be triggered at a time by an event on a signal in the sensitivity list.  ... 
doi:10.1109/rme.2008.4595747 fatcat:y7p3ujfoqveb5grdq3bbowscbu

An Automated Continuous Integration Multitest Platform for Automotive Systems

Boyang Du, Sarah Azimi, Annarita Moramarco, Davide Sabena, Filippo Parisi, Luca Sterpone
2021 IEEE Systems Journal  
For a complicated and/or complex system, tests are preferred to be carried out in different stages of the development process and as early as possible to avoid extra costs due to the errors caught at later  ...  In this article, we present a testing framework utilizing the continuous integration (CI) solution from software engineering, a commercial virtual platform, and a hardware field programmable gate array  ...  The developed platform has been compared in timing performance on executing a functional system test and resolution of the monitored signals.  ... 
doi:10.1109/jsyst.2021.3069548 fatcat:j6di3pe6b5bzvbec7kj3btue3e

Hardware Trojan Detection Using Controlled Circuit Aging

Virinchi Roy Surabhi, Prashanth Krishnamurthy, Hussam Amrouch, Kanad Basu, Jorg Henkel, Ramesh Karri, Farshad Khorrami
2020 IEEE Access  
Hardware Trojans, which are typically triggered by rare events, may alter function, deny service, or leak information.  ...  Aging-Induced Timing Errors: The delay of a transistor is proportional to its current in the ON state (I ON ). I ON is a function of the threshold voltage and the carrier mobility as in Eq. 1 [22] .  ...  His research work is focused on co-design for embedded hardware/software systems with respect to power, thermal and reliability aspects.  ... 
doi:10.1109/access.2020.2989735 fatcat:lefwri5cqjeh7ghi3vk3jpoaku

Trojan Counteraction in Hardware: A Survey and New Taxonomy

Bazzazi Amin, Shalmani Mohammad TaghiManzuri, Hemmattyar Ali Mohammad Afshin
2016 Indian Journal of Science and Technology  
Both in factories manufacturing and later at actual operation, digital integrated circuits (IC) might encounter a variety of hardware attacks, one type of which involves Hardware Trojans (HT).  ...  In this regard, the first step is to understand the taxonomy of Trojans and the current ways in which they can be encountered. For that purpose, certain classifications are required.  ...  In sum, HTs can operate in three ways: 1) Alter the main design function in certain conditions, 2) Activate at a certain time and deactivate the entire system, and 3) Steal important system information  ... 
doi:10.17485/ijst/2016/v9i18/93764 fatcat:jneq2owtnfhapmwcknbzprx6nq


Markus Becker, Daniel Baldin, Christoph Kuznik, Mabel Mary Joy, Tao Xie, Wolfgang Mueller
2012 Proceedings of the tenth ACM international conference on Embedded software - EMSOFT '12  
We apply an extension of the QEMU software emulator, which injects mutations at run-time by dynamic code translation without affecting the binary software under test.  ...  This paper presents the XEMU framework for mutation based testing of embedded software binaries.  ...  They introduced a generic instrumentation interface for QEMU that is based on event-triggered plug-ins.  ... 
doi:10.1145/2380356.2380368 dblp:conf/emsoft/BeckerBKJX012 fatcat:qtklzofhsva7jgd4i453h4hhci

Hardware Security in IoT Devices with Emphasis on Hardware Trojans

Simranjeet Sidhu, Bassam J. Mohd, Thaier Hayajneh
2019 Journal of Sensor and Actuator Networks  
This paper emphasizes the need for a secure hardware-level foundation for security of these devices, as depending on software security alone is not adequate enough.  ...  However, implementation of hardware security in these devices has been overlooked, and many researches have mainly focused on software, network, and cloud security.  ...  B.J.M. was responsible for guiding the hardware security part, helped in the security analysis and writing the paper.  ... 
doi:10.3390/jsan8030042 fatcat:zuzw6sf2hzgdfiz65p2joz2g6a

A Survey on Network Verification and Testing with Formal Methods: Approaches and Challenges

Yahui Li, Xia Yin, Zhiliang Wang, Jiangyuan Yao, Xingang Shi, Jianping Wu, Han Zhang, Qing Wang
2018 IEEE Communications Surveys and Tutorials  
Furthermore, techniques ranging from formal modeling to verification and testing have been applied to help operators build reliable systems in electronic design automation and software.  ...  We perform a comprehensive survey on well-developed methodologies and tools for data plane verification, control plane verification, data plane testing and control plane testing.  ...  ACKNOWLEDGMENT The authors thank the anonymous reviewers for their suggestions.  ... 
doi:10.1109/comst.2018.2868050 fatcat:h3op4heca5d75bpokfsbfevnwe

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA [article]

Johann Knechtel, Elif Bilge Kavun, Francesco Regazzoni, Annelie Heuser, Anupam Chattopadhyay, Debdeep Mukhopadhyay, Soumyajit Dey, Yunsi Fei, Yaacov Belenky, Itamar Levi, Tim Güneysu, Patrick Schaumont, Ilia Polian
2020 arXiv   pre-print
In this paper, we first introduce hardware security for the EDA community. Next we review prior (academic) art for EDA-driven security evaluation and implementation of countermeasures.  ...  Electronic design automation (EDA) for ICs has focused traditionally on power, performance, and area.  ...  While there are works on automated synthesis of masking for software [44] , EDA-centric approaches for hardware are still in development.  ... 
arXiv:2001.09672v1 fatcat:72lodqrfhfeanfnatkzkjuoc2i

A Flexible Software-Based Framework for Online Detection of Hardware Defects

Kypros Constantinides, Onur Mutlu, Todd Austin, Valeria Bertacco
2009 IEEE transactions on computers  
The software nature of our framework makes it flexible: testing techniques can be modified/upgraded in the field to trade-off performance with reliability without requiring any change to the hardware.  ...  When a hardware defect is present, these tests can diagnose and locate it, and then activate system repair through resource reconfiguration.  ...  ACKNOWLEDGMENTS The authors thank the anonymous reviewers for their feedback.  ... 
doi:10.1109/tc.2009.52 fatcat:geriayi2sfdnjcld66odhmc4hu

Test Strategies for Reliable Runtime Reconfigurable Architectures

Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Eric Schneider, Hongyan Zhang, Jorg Henkel, Hans-Joachim Wunderlich
2013 IEEE transactions on computers  
During operation, PORT is used to periodically check the reconfigured hardware units for malfunctions in the programmable logic.  ...  The reliability of FPGAs, being manufactured in latest technologies, is threatened by soft errors, as well as aging effects and latent defects.  ...  ACKNOWLEDGMENTS This work is supported in parts by the German Research Foundation (DFG) as part of the priority program "Dependable Embedded Systems" (SPP 1500  ... 
doi:10.1109/tc.2013.53 fatcat:5trm6425ovctfebp7sxwjttyqy

Optimal Periodic Testing of Intermittent Faults In Embedded Pipelined Processor Applications

N. Kranitis, A. Merentitis, N. Laoutaris, G. Theodorou, A. Paschalis, D. Gizopoulos, C. Halatsis
2006 Proceedings of the Design Automation & Test in Europe Conference  
Since Software-Based Self-Test (SBST) has been proposed as an effective strategy for on-line testing of processors integrated in non-safety critical low-cost embedded system applications, optimal test  ...  Then, we present for the first time an enhanced SBST strategy for on-line testing of complex pipelined embedded processors.  ...  Software-Based Self-Test (SBST) has been proposed as an effective strategy for on-line testing of processors integrated in non-safety critical low-cost embedded system applications [8] .  ... 
doi:10.1109/date.2006.243983 dblp:conf/date/KranitisMLTPGH06 fatcat:ivoxgbsanbhmniqim66imwpty4

On Reliability Trojan Injection and Detection

Aswin Sreedhar, Sandip Kundu, Israel Koren
2012 Journal of Low Power Electronics  
In this paper we present examples of such reliability Trojans and describe testing approaches for detecting these reliability tampering attempts.  ...  Hardware design houses are increasingly outsourcing designs to be manufactured by cheaper fabrication facilities due to economic factors and market forces.  ...  for rare event nodes in this experiment.  ... 
doi:10.1166/jolpe.2012.1225 fatcat:4uesxkklyjf7jlj6qkjbfkiy6m

A Survey of Aging Monitors and Reconfiguration Techniques [article]

Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm Moraes
2020 arXiv   pre-print
Furthermore, most of the literature contributions are in the digital field, using hardware solutions for monitoring aging in circuits.  ...  Results show that the most common monitor type used for aging detection is to monitor timing errors, and the most common reconfiguration technique used to deal with aging is voltage scaling.  ...  [40] propose an aging monitor based on hardware and software.  ... 
arXiv:2007.07829v1 fatcat:2syuq4acm5ci3kafbxljvzbguq
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