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AMULET3: a 100 MIPS asynchronous embedded processor
Proceedings 2000 International Conference on Computer Design
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AMULET3 is a 32-bit asynchronous processor core that is fully instruction set compatible with the clocked ARM cores. ...
AMULET3 shows that asynchronous technology is commercially viable, and is competitive in terms of performance, area and power-efJiciency with clocked design. ...
The memory system reduces the maximum throughput to 100 MIPS at 215 mW; the overall system power-efficiency is 465 M I P S N . ...
doi:10.1109/iccd.2000.878304
dblp:conf/iccd/FurberEG00
fatcat:gdmxbpig3jgsbk3aewdatgnlie
Power management in the Amulet microprocessors
2001
IEEE Design & Test of Computers
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100 million instructions per second. ...
Their asynchronous control framework has positive benefits for low-power applications because it reduces activity to the minimum required to perform a task, whereas a clock inevitably incurs wasteful activity ...
Amulet3 halt A halting mechanism very similar to that used in Amulet2 is employed in Amulet3. A branch instruction that loops to itself is detected, and the processor stops. ...
doi:10.1109/54.914617
fatcat:foz67mcyprcrzlaype3oennxy4
AMULET3 revealed
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems
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AMULET3 is the third fully asynchronous implementation of the ARM architecture designed at the University of Manchester. ...
Most notable among the changes are the use of a Harvard architecture to increase memory bandwidth and the inclusion of a reorder buffer to handle data forwarding and memory faults. ...
This implies a performance target of well over 100 MIPS (measured with Dhrystone 2.1), compared to the 40 MIPS delivered by AMULET2e on a 0.5 µm process. ...
doi:10.1109/async.1999.761522
dblp:conf/async/GarsideFC99
fatcat:yapgf6flljh3flmmgkfhnft7om
The Amulet chips: Architectural development for asynchronous microprocessors
2009
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)
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The objective was to demonstrate that it was feasible to implement a commercial architecture with asynchronous logic and that certain advantages could be gained from a self-timed processor. ...
During the 1990s a series of asynchronous microprocessors based on the ARM architecture was developed at the University of Manchester. ...
Delivered in 2000 on a 0.35 μm process the processor provided over 100 MIPS -the same as a contemporary ARM9. ...
doi:10.1109/icecs.2009.5411006
dblp:conf/icecsys/GarsideFTW09
fatcat:rptz35hfbfc5rdznpbtsirvwbi
AMULET3: a high-performance self-timed ARM microprocessor
Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)
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AMULET3 is a fully asynchronous implementation of ARM architecture v4T and was designed at the University of Manchester between 1996 and. ...
It is the third generation asynchronous ARM, and is aimed at a significantly higher performance level than its predecessors. ...
This implies a performance target of well over 100 MIPS (measured with Dhrystone 2.1) on a 0.35 µm process, compared to the 40 MIPS delivered by AMULET2e on a 0.5 µm process. ...
doi:10.1109/iccd.1998.727058
dblp:conf/iccd/FurberGG98
fatcat:tvsrwovslzfidofkj7rty3bpuq
Towards Designing Asynchronous Microprocessors: From Specification to Tape-out
2019
IEEE Access
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Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing ...
mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. ...
is a 100 MIPS asynchronous embedded processor based Harvard architecture. ...
doi:10.1109/access.2019.2903126
fatcat:rwtsay62xbenhn5cgwzszhf4lm
Characterization and synthesis of a 32-bit asynchronous microprocessor in synchronous reconfigurable devices
2015
Journal of Applied Research and Technology
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The performance obtained was 4 MIPS for the asynchronous microprocessor against 1.6 MIPS for the synchronous. All Rights Reserved ...
This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronous reconfigurable device (FPGA), taking advantage of a hard macro. ...
)
2-phase, dual rail, 5-stage pipeline, based on
a 32-bit MIPS R 3000.
496,000 0.5 m transistors
52.3 VAX MIPS
AMULET3 (Furber, Edwards, & Garside,
2000)
4-phase, single rail, forwarding pipeline ...
doi:10.1016/j.jart.2015.10.004
fatcat:6av7fyhyqnholitoeeimvgd3iy
AMULET3i-an asynchronous system-on-chip
Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)
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As such it is capable of forming the core of a wide range of system-on-chip applications, bringing asynchronous design into commercial use in a flexible and easy-to-use configuration. ...
AMULET3i is the third generation asynchronous ARMcompatible microprocessor subsystem developed at the University of Manchester. ...
The ARM9 processor core achieves 800 MIPS/W. ...
doi:10.1109/async.2000.836999
dblp:conf/async/GarsideBBCEFLMPTWLP00
fatcat:uhdy6xqszbcgnofrd74463kdkm
AMULET3i cache architecture
Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001
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The design has been optimised for the AMULET3 asynchronous microprocessor core, but the techniques developed are much more widely applicable. ...
This paper presents an evaluation of a range of cache features applied to an asynchronous, dual-ported copyback cache. ...
The primary interest in this work is in cache architecture for embedded processors, but many of the techniques developed should be applicable to larger, high-performance asynchronous caches. ...
doi:10.1109/async.2001.914079
dblp:conf/async/HormdeeG01
fatcat:byry4oxdljfhzbw7bvmc6sxaje
Adaptive pipeline depth control for processor power-management
Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors
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Two techniques are shown using an existing asynchronous processor as a starting point. ...
A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. ...
A. Efthymiou is supported by the Department of Computer Science, University of Manchester. This support is gratefully appreciated. ...
doi:10.1109/iccd.2002.1106812
dblp:conf/iccd/EfthymiouG02
fatcat:d64x67dspfgvpfpagpwjvyl5ku
SPA - a synthesisable Amulet core for smartcard applications
Proceedings Eighth International Symposium on Asynchronous Circuits and Systems
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SPA is a synthesised, self-timed, ARM-compatible processor core. The use of synthesis was mandated by a need for rapid implementation. ...
A complete system-on-chip is being synthesised with a only small amount of hand design being employed to boost the throughput of the on-chip interconnection system. ...
Amulet3 [14] is a 100 MIPS core on a 0.35µm CMOS technology. ...
doi:10.1109/async.2002.1000310
dblp:conf/async/BainbridgeBTGRP02
fatcat:zttp5jpkhrf7bjrafttegt7iqi