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AEGIS

G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas
2014 25th Anniversary International Conference on Supercomputing Anniversary Volume -  
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks.  ...  We also describe a variant implementation assuming an untrusted operating system. aegis provides users with tamper-evident, authenticated environments in which any physical or software tampering by an  ...  We would also like to thank Ron Rivest and Krste Asanovic for many constructive comments, as well as all the members of our group who helped proof-read this paper.  ... 
doi:10.1145/2591635.2667184 fatcat:vsxhymcelfbr3pjbxnt2upkw44

AEGIS

G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas
2003 Proceedings of the 17th annual international conference on Supercomputing - ICS '03  
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks.  ...  adversary is guaranteed to be detected, and private and authenticated tamper-resistant environments where additionally the adversary is unable to obtain any information about software or data by tampering  ...  We would also like to thank Ron Rivest and Krste Asanovic for many constructive comments, as well as all the members of our group who helped proof-read this paper.  ... 
doi:10.1145/782814.782838 dblp:conf/ics/SuhCGDD03 fatcat:qxgo3jshfng5vkowxbifl7go44

AEGIS: A single-chip secure processor

G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas
2005 Information Security Technical Report  
This article presents the AEGIS secure processor architecture, which enables new applications by ensuring private and authentic program execution even in the face of physical attack.  ...  Our architecture uses two new primitives to achieve physical security.  ...  Private Tamper-Resistant (PTR) mode which additionally ensures privacy, and a Suspended Secure Processing (SSP) mode.  ... 
doi:10.1016/j.istr.2005.05.002 fatcat:fs4yl5r63ba5tlciuudzw67oha

Aegis: A Single-Chip Secure Processor

G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas
2007 IEEE Design & Test of Computers  
) & standard (STD), which has no additional security measures; & tamper evident (TE), which ensures program state integrity; & private tamper-resistant (PTR), which additionally ensures privacy; and&  ...  However, providing high-grade tamper resistance can be expensive, 4 and active intrusion detection circuitry must be continuously battery powered even when the device is off.  ...  His research interests include secure embedded processors, architectural techniques for security and verification, and new programmable substrates for simplified synthesis.  ... 
doi:10.1109/mdt.2007.179 fatcat:nkirz46au5d7jkc7w5sdjgwheu

Aegis: A single-chip secure processor

G. Suh, Charles O'Donnell, Srinivas Devadas
2007 IEEE Design & Test of Computers  
AEGIS, with its off-chip protection mechanisms, is slower than traditional processors by 26% on average for large applications and by a few percent for embedded applications.  ...  The architecture suggests a technique called suspended secure processing to allow a secure part of an application to be protected separately from the rest.  ...  mode, private tamper-resistant (PTR) mode, and suspended secure processing (SSP) mode (see Chapter 2).  ... 
doi:10.1109/mdt.2007.4343587 fatcat:qzwlnqrklvat5kgjzia7yed47q

Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions

G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas
2005 SIGARCH Computer Architecture News  
In this paper we present the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs.  ...  Our architecture gives applications the flexibility of trusting and protecting only a portion of a given process, unlike prior proposals which require a process to be protected in entirety.  ...  (This reduces the amount of code which is run with any inherent overheads of tamper-evident or tamper-resistant security.)  ... 
doi:10.1145/1080695.1069974 fatcat:ghxqvdd4cnhe7gzxrz7mhg4hxu

A Flexible Design Flow for Software IP Binding in FPGA

Michael A. Gora, Abhranil Maiti, Patrick Schaumont
2010 IEEE Transactions on Industrial Informatics  
This work proposes a novel design flow for SWIP binding on a commodity FPGA platform lacking specialized hardcore security facilities.  ...  As a result, developers want to ensure that their Software Intellectual Property (SWIP) is protected from being exposed to or tampered with by unauthorized parties.  ...  AEGIS provides for a single-chip processor with built-in tamper resistance and detection as well as dedicated cryptographic components.  ... 
doi:10.1109/tii.2010.2068303 fatcat:uqp4j6jztjag7koa7mvid3t37q

Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions

G.E. Suh, C.W. O'Donnell, I. Sachdev, S. Devadas
32nd International Symposium on Computer Architecture (ISCA'05)  
In this paper we present the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs.  ...  Our architecture gives applications the flexibility of trusting and protecting only a portion of a given process, unlike prior proposals which require a process to be protected in entirety.  ...  (This reduces the amount of code which is run with any inherent overheads of tamper-evident or tamper-resistant security.)  ... 
doi:10.1109/isca.2005.22 dblp:conf/isca/SuhOSD05 fatcat:xhedgrinvndhjfa4ejbgjzx35e

User Centric Security Model for Tamper-Resistant Devices

Raja Naeem Akram, Konstantinos Markantonakis, Keith Mayes
2011 2011 IEEE 8th International Conference on e-Business Engineering  
Tamper-evident: The device has the capability to detect potential tampering with the hardware and respond in a pre-dened manner. 2.3 Candidates for User Centric Tamper-Resistant Device Yes Note.  ...  The PRNG mechanism is not tamper-evident and it relies on the tamper-resistant mechanisms of the smart card to provide physical security.  ...  In this section, we detail the SP's implementation of the STCP ACA and the helper functions utlised during the STCP SP are discussed in appendices C. 11 .1 and C. 11 C.9.1 Initiator Smart Card  ... 
doi:10.1109/icebe.2011.69 dblp:conf/icebe/AkramMM11 fatcat:iqgqkfhjnfhphcbn5ultrlf2li

Micro-Architecture Support for Integrity Measurement on Dynamic Instruction Trace

Hui Lin, Gyungho Lee
2010 Journal of Information Security  
Overhead in terms of circuit area, power consumption, and access time, is less than 3% for most criterions. And system only introduces less than 2% performance overhead in average.  ...  For DiT, processor's instruction cache is modified to stores back instructions to memory.  ...  Figure 1 makes a comparison between three measurement mechanisms: DiT proposed in this paper, IMA and Aegis which is a typical secure processor design to achieve tamper evidence and resistance environment  ... 
doi:10.4236/jis.2010.11001 fatcat:b4xk3fosyndyfiwy4ecskmov2m

Bootstrapping Trust in Commodity Computers

Bryan Parno, Jonathan M. McCune, Adrian Perrig
2010 2010 IEEE Symposium on Security and Privacy  
This approach unifies disparate research efforts and highlights opportunities for additional work that can guide real-world improvements in computer security.  ...  is not infected with malware) and for communicating a remote computer's state (e.g., to enable the user to check that a web server will adequately protect her data).  ...  Acknowledgements The authors are grateful to Virgil Gligor for stimulating discussions, and to Reiner Sailer, Ron Perez, and the anonymous reviewers for their insightful comments.  ... 
doi:10.1109/sp.2010.32 dblp:conf/sp/ParnoMP10 fatcat:knwcyutj2ndhba7wdrazkn4nbu

A flexible design flow for software IP binding in commodity FPGA

Michael A. Gora, Abhranil Maiti, Patrick Schaumont
2009 2009 IEEE International Symposium on Industrial Embedded Systems  
As a result, developers want to ensure that their SWIP sources are protected from being exposed to an unauthorized party and are restricted to run only on a trusted FPGA platform. 978-1-4244-4110-5/09/  ...  The AEGIS provides for a single-chip processor with built-in tamper resistance and detection as well dedicated cryptographic components. AEGIS is however an ASIC solution.  ...  Tamper resistance allows a program to validate its own integrity and to cease operation if it has been modified [17, 18, 19] .  ... 
doi:10.1109/sies.2009.5196217 dblp:conf/sies/GoraMS09 fatcat:ya2do63yj5b5pk5gkeworkeomq

Trusted Computing: Security and Applications

Eimear Gallery, Chris J. Mitchell
2009 Cryptologia  
This paper is an attempt to encourage greater debate about this technology and its possible implications.  ...  The main objective of this paper is to highlight some of the major security and application issues confronting trusted computing technology.  ...  We would like to thank Stéphane Lo Presti and other partners in the OpenTC project for valuable guidance and advice over the last couple of years.  ... 
doi:10.1080/01611190802231140 fatcat:slr52mewqrbxtg6orjxes4valy

Accountability in hosted virtual networks

Eric Keller, Ruby B. Lee, Jennifer Rexford
2009 Proceedings of the 1st ACM workshop on Virtualized infrastructure systems and architectures - VISA '09  
For each, we provide a description of an architecture that can be achieved with technology available today, the limitations of that architecture, and then propose an extension which overcomes the limitations  ...  Virtualization enables multiple networks, each customized for a particular purpose, to run concurrently over a shared substrate.  ...  the first place by ensuring that the software is resistant to tampering.  ... 
doi:10.1145/1592648.1592654 dblp:conf/sigcomm/KellerLR09 fatcat:32d3vehkdjfa7j5ojhh7rk67cq

Hardware and Security [chapter]

Gedare Bloom, Eugen Leontie, Bhagirath Narahari, Rahul Simha
2012 Handbook on Securing Cyber-Physical Critical Infrastructure  
The AEGIS [110] architecture greatly improves on XOM, its predecessor, and presents techniques for control-flow protection, privacy, and prevention of data tampering.  ...  Examples include the XOM architecture [105] and several other tamper-resistant processors [106, 107] ; these techniques require re-design of the processor.  ... 
doi:10.1016/b978-0-12-415815-3.00012-1 fatcat:usk6j5webjdytjmtjublkukjve
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