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A unified distance transform algorithm and architecture

David W. Paglieroni
1992 Machine Vision and Applications  
Erratum "A Unified Distance Transform Algorithm and Architecture" (Machine Vision and Applications, Volume 5, Number 2) David W.  ...  ), cannot be used to generate nearest feature transforms (FT's) or equivalently, signed distance transforms (SDT's).  ... 
doi:10.1007/bf02627003 fatcat:ontdiad4gbasdl4xugsifcssh4

Scene Transformer: A unified architecture for predicting multiple agent trajectories [article]

Jiquan Ngiam, Benjamin Caine, Vijay Vasudevan, Zhengdong Zhang, Hao-Tien Lewis Chiang, Jeffrey Ling, Rebecca Roelofs, Alex Bewley, Chenxi Liu, Ashish Venugopal, David Weiss, Ben Sapp (+2 others)
2022 arXiv   pre-print
Through combining a scene-centric approach, agent permutation equivariant model, and a sequence masking strategy, we show that our model can unify a variety of motion prediction tasks from joint motion  ...  Our model architecture employs attention to combine features across road elements, agent interactions, and time steps.  ...  DISCUSSION We propose a unified architecture for autonomous driving that is able to model the complex interactions of agents in the environment.  ... 
arXiv:2106.08417v3 fatcat:rj7xuncobzedxjo6fo26ish5q4

A Systematic Hardware Sharing Method for Unified Architecture Design of H.264 Transforms

Po-Hung Chen, Hung-Ming Chen, Ing-Chao Lin
2015 Mathematical Problems in Engineering  
Secondly, the proposed architecture-unification technique further unifies these six transform architectures into a low cost hardware-unified architecture.  ...  In order to demonstrate the effectiveness of the method, a unified architecture is designed using the method for all of the six transforms involved in the H.264 video codec: 2D 4 × 4 forward and inverse  ...  Figure 12 : 12 The unified architecture for all H.264 transforms. Architecture for a 1D 8 × 8 Inverse Integer Transform.  ... 
doi:10.1155/2015/258613 fatcat:z366lwzrlfdc3nqf5wuaz6th6m

A unifying framework for iteration reordering transformations

W. Kelly, W. Pugh
Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing  
We present a framework for unifying iteration reordering transformations such as loop interchange, loop distribution, skewing, tiling, index set splitting and statement reordering.  ...  The framework is based on the idea that a transformation can be represented as a mapping from the original iteration space to a new iteration space.  ...  Conclusions We have presented a framework for unifying reordering transformations such as loop interchange, distribution, skewing, tiling, index set splitting and statement reordering.  ... 
doi:10.1109/icapp.1995.472180 fatcat:xksx4s7wkne3ngbfrrpjekvvta

Optimal unified IIR architectures for time-recursive discrete sinusoidal transforms

K.J.R. Liu, C.T. Chiu, R.K. Kolagotla, J.F. JaJa
1993 IEEE International Conference on Acoustics Speech and Signal Processing  
An optimal unified architecture that can efficiently compute the Discrete Cosine, Sine, Hartley, Fourier, Lapped Orthogonal, and Complex Lapped transforms for a continuous input data stream is proposed  ...  We provide a theoretical justification by showing that any discrete transform whose basis functions satisfy the Fundamental Recurrence Formula has a second-orider autoregressive structure in its filter  ...  CONCLUSIONS In this paper, we present a new optimal unified architecture to compute the discrete sinusoidal transforms.  ... 
doi:10.1109/icassp.1993.319438 dblp:conf/icassp/LiuCKJ93 fatcat:ooh2u7aiejhdld4dpl2fetwzzi

UniNet: Unified Architecture Search with Convolution, Transformer, and MLP [article]

Jihao Liu and Hongsheng Li and Guanglu Song and Xin Huang and Yu Liu
2021 arXiv   pre-print
Notably, Our searched network UniNet (Unified Network) outperforms state-of-the-art pure convolution-based architecture, EfficientNet, and pure transformer-based architecture, Swin-Transformer, on multiple  ...  To this end, we jointly search all operators and down-sampling modules in a unified search space.  ...  MODELING CONVOLUTION, ATTENTION, MLP WITH A UNIFIED SEARCHABLE FORM Recently, transformer and MLP based architectures are able to achieve comparable performance with convolution-based ones on general visual  ... 
arXiv:2110.04035v1 fatcat:e2nadl3swzctlcsxyqs67jqsue

Design of Unified Inverse Transformer for HEVC and VP9
HEVC 및 VP9 겸용 통합 역변환기의 설계

Seulkee Jung, Seongsoo Lee
2015 Journal of IKEEE  
In this paper, a unified inverse transformer is designed for HEVC and VP9.  ...  The proposed architecture performs all modes of HEVC and VP9 in the unified inverser transformer, such as 4×4~32×32 HEVC IDCT, 4×4 HEVC IDST, 4×4~32×32 VP9 IDCT, 4×4~16×16 VP9 IADST and 4×4 IWHT.  ...  Design of Unified Inverse Transformer for HEVC and VP9 141 (600) Fig. 6. 8×8 unified inverse transform block architecture 그림 6. 8×8 통합 역변환기 블록 아키텍쳐 Fig. 7. 16×16 unified inverse transform block  ... 
doi:10.7471/ikeee.2015.19.4.596 fatcat:o4gdmeuqh5h4fasdo6chp56nwm

Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST

D.F. Chiper, M.N.S. Swamy, M.O. Ahmad, T. Stouraitis
2005 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
In this paper, an efficient design approach for a unified very large-scale integration (VLSI) implementation of the discrete cosine transform /discrete sine transform /inverse discrete cosine transform  ...  This formulation allows an efficient memory-based systolic array implementation of the unified architecture using dual-port ROMs and appropriate hardware sharing methods.  ...  CONCLUSION In this paper, we have presented a unified architecture for DCT/DST/IDCT/IDST by appropriately formulating the four transforms into cyclic convolution structures in a unified manner.  ... 
doi:10.1109/tcsi.2005.849109 fatcat:gl43cyqpgvespjjkfdrtp4bwo4

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

Doru Florin Chiper, Laura-Teodora Cotorobai
2021 Electronics  
The proposed method introduces a new approach in obtaining a unified VLSI architecture for computing type IV discrete cosine transform (DCT-IV) and type IV discrete sine transform (DST-IV), with an efficient  ...  A very efficient, unified VLSI architecture for type IV DCT/DST can be obtained, which allows the computation of the two algorithms on the same hardware, allowing an efficient incorporation of the obfuscation  ...  It is possible to have a unified algorithm for computing more than one transform.  ... 
doi:10.3390/electronics10141656 fatcat:wmz7xsafr5h2rbdknvh54mrawq

High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems

Tiago Dias, Sebastian Lopez, Nuno Roma, Leonel Sousa
2011 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
Furthermore, such results also showed that this architecture can compute, in realtime, all the above mentioned H.264/AVC transforms for video sequences with resolutions up to UHDV.  ...  This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute the 4×4 forward/inverse integer DCT, as well as the 2-D 4 × 4 / 2 × 2 Hadamard transforms.  ...  CONCLUSIONS In this paper, a novel high throughput and scalable architecture for unified transform coding in H.264/AVC was presented.  ... 
doi:10.1109/samos.2011.6045465 dblp:conf/samos/DiasLRS11 fatcat:kqpxrpfvrjdxrmqozytpusbeya

Efficient Hardware Architecture Of The Direct 2- D Transform For The Hevc Standard

Fatma Belghith, Hassen Loukil, Nouri Masmoudi
2013 Zenodo  
This paper presents the hardware design of a unified architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional (2-D) transform for the HEVC standard.  ...  This architecture is based on fast integer transform algorithms. It is designed only with adders and shifts in order to reduce the hardware cost significantly.  ...  CONCLUSION In this paper, we proposed a unified architecture of the twodimensional transform using with the Modified Integer Transform.  ... 
doi:10.5281/zenodo.1083161 fatcat:dw5knzojdzhyrpgqbtubp7dksa

Hardware Acceleration of Approximate Transform Module for the Versatile Video Coding Standard

Ahmed Kammoun, Wassim Hamidouche, Pierrick Philipp, Fatma Belghith, Nouri Massmoudi, Jean-Francois Nezan
2019 2019 27th European Signal Processing Conference (EUSIPCO)  
The architecture design includes a pipelined and reconfigurable forward-inverse DCT-II core transform.  ...  A unified 2D implementation of 16 and 32-point forward-inverse DCT-II, approximate DST-VII and DCT-VIII is also presented.  ...  Fig 1 illustrates the proposed architecture of the unified DCT-IDCT core transform.  ... 
doi:10.23919/eusipco.2019.8902594 dblp:conf/eusipco/KammounHPBMN19 fatcat:bsvusnawxzbkjhu6kx3nukuh3m

A Reconfigurable Computing Engine for Wavelet Transforms

Kang Sun, Xuezeng Pan, Lingdi Ping
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
In this paper, a unified computation framework for discrete and continuous wavelet transform based on lifting scheme and a reconfigurable architecture that includes reconfigurable lifting step arrays and  ...  Due to the high performance and flexibility of reconfigurable computing systems, it is very attractive to design a reconfigurable architecture for discrete and continuous wavelet transform of wide range  ...  So, it is possible to build a unified lifting scheme framework for reconfigurable computing of discrete and continuous wavelet transforms.  ... 
doi:10.1109/ipdps.2007.370373 dblp:conf/ipps/SunPP07 fatcat:444qib7shndl7ar7tostu6funi

Unified array architecture for discrete cosine transform, sine transform and their inverses

Jiun-In Guo, Chein-Wei Jen, Chingson Chen
1995 Electronics Letters  
A unified array design for the discrete cosine transform, discrete sine transform and their inverses based on a new general formulation is presented.  ...  We present a unified array design for the DCT, DST, and their inverses according to a new general formulation.  ... 
doi:10.1049/el:19951254 fatcat:6a6lt4tgy5hohh23nn2g5akp5a

A Low-Power and High Throughput Reconfigurable Data Integrity Unit for Software Radio

L. Thulasimani, M. Madheswaran
2010 International Journal of Computer and Electrical Engineering  
, Reconfigurability, SHA-192, Unified architecture, Hardware utilization.  ...  The hash algorithms MD-5, SHA-1, and the unified architecture of MD-5and SHA-192 have been implemented using Verilog, and their hardware utilization on the FPGA device is being compared Index Terms-SDR  ...  shown in Figure 5 . 5 Data Transformation Of Unified Architecture Figure 6 . 6 Area, frequency, power comparison.  ... 
doi:10.7763/ijcee.2010.v2.221 fatcat:grtnilu6fbg7davm46zjeaf6z4
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