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Variable Length Reconfigurable Algorithms and Architectures for DCT/IDCT Based on Modified Unfolded Cordic

Liyi Xiao
<span title="2013-06-14">2013</span> <i title="Bentham Science Publishers Ltd."> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/536reesyujf2dkefhg3lcz4jwe" style="color: black;">Open Electrical &amp; Electronic Engineering Journal</a> </i> &nbsp;
Furthermore, the proposed architectures have higher regularity, modularity, computation accuracy and suitable for VLSI implementation.  ...  A coordinate rotation digital computer (CORDIC) based variable length reconfigurable DCT/IDCT algorithm and corresponding architecture are proposed.  ...  CORDIC-based architectures are suitable for VLSI implementation with regularity and simple hardware architecture.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.2174/1874129001307010071">doi:10.2174/1874129001307010071</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gtbifhqzzfcmzkpktmslyaunga">fatcat:gtbifhqzzfcmzkpktmslyaunga</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180722135904/https://benthamopen.com/contents/pdf/TOEEJ/TOEEJ-7-71.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c6/52/c652cb345b050fd3cdb02a81267d73dae1db4e4d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.2174/1874129001307010071"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Effective Hardware Accelerator for 2D DCT/IDCT Using Improved Loeffler Architecture

Zhiwei Zhou, Zhongliang Pan
<span title="">2022</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/q7qi7j4ckfac7ehf3mjbso4hne" style="color: black;">IEEE Access</a> </i> &nbsp;
Only 33 cycles are required to complete the 8×8 blocks of 2D DCT/IDCT, which can be used as a high-performance hardware accelerator for image and video compression encoding.  ...  The FPGA implementation of the proposed architecture uses a Virtex-7 XC7VX330T device, running at 288 MHz with a throughput of 558 M Pixel/sec, and a Full HD real-time frame rate of up to 269 fps.  ...  [26] proposed a 2D 8×8 DCT/IDCT VLSI full-pipeline less multiplication architecture, running at a frequency of 166 MHz with a latency of 65 clock cycles. Xing et al.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/access.2022.3146162">doi:10.1109/access.2022.3146162</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/qyfn6uypsrg2lponubniwnzc6u">fatcat:qyfn6uypsrg2lponubniwnzc6u</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20220129163737/https://ieeexplore.ieee.org/ielx7/6287639/6514899/09691351.pdf?tp=&amp;arnumber=9691351&amp;isnumber=6514899&amp;ref=" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/bb/4d/bb4dde0d31575472be1a7ad1a716373d15ed2598.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/access.2022.3146162"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> ieee.com </button> </a>

A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards

Sha Shen, Weiwei Shen, Yibo Fan, Xiaoyang Zeng
<span title="">2012</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/pmefrmqsezb5zd3w7pf5k7fmxu" style="color: black;">2012 IEEE International Conference on Multimedia and Expo</a> </i> &nbsp;
To fulfill this requirement, this work proposes a fast computational algorithm of large size integer IDCT. A unified VLSI architecture for 4/8/16/32-point integer IDCT is also proposed accordingly.  ...  Multiplierless MCM (Multiple Constant Multiplication) is used for 4/8-point IDCT. The regular multipliers and sharing technique are used for 16/32-point IDCT.  ...  VLSI ARCHITECTURE FOR UNIFIED 1D IDCT In this section, the unified VLSI architecture for 1D integer IDCT is proposed according to the signal flow which is shown in Fig. 2 .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/icme.2012.7">doi:10.1109/icme.2012.7</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/icmcs/ShenSFZ12.html">dblp:conf/icmcs/ShenSFZ12</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/m7qfjyaplfdv5j46i6iwazgsum">fatcat:m7qfjyaplfdv5j46i6iwazgsum</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809033120/http://www.cmlab.csie.ntu.edu.tw/~zenic/Data/Download/ICME2012/Conference/data/4711a788.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/78/4c/784c2add49cff5fb026d4a64448cabba18d94b12.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/icme.2012.7"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

On the realization of discrete cosine transform using the distributed arithmetic

Y.-H. Chan, W.-C. Siu
<span title="">1992</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/a2sy5llz7rchfdd7zku3k2hthy" style="color: black;">IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications</a> </i> &nbsp;
In such a case, typical convolvers can be used as the core unit for the hardware implementation of the transforms. Hence, an efficient unified DCT/IDCT chip can be designed.  ...  A 2-D 11 X 11 unified DCT/IDCT chip is also proposed to demonstrate the superiority of the proposed formulation in this paper.  ...  This provides a straightforward but ideal solution for the VLSI implementation of a unified DCT/IDCT chip by making use of the distributed arithmetic. g(qk)C(q).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/81.250161">doi:10.1109/81.250161</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/2swwvqhk2rac5nw6ap322r4ojq">fatcat:2swwvqhk2rac5nw6ap322r4ojq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170811153230/http://ira.lib.polyu.edu.hk/bitstream/10397/1539/1/Realization%20discrete%20cosine%20transform_92.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ab/38/ab38c716f7484fdbedab711266e7848f4902c3ba.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/81.250161"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation

Tze-yun Sung, Yaw-shih Shieh, Chun-wang Yu, Hsi-chin Hsin
<span title="">2006</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/6rmfmj3lu5bnba77hqv4pszbgi" style="color: black;">2006 Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT&#39;06)</a> </i> &nbsp;
In this paper, efficient architectures with parallel and pipelined structures are proposed to implement 8 8 × DCT and IDCT processors.  ...  The proposed architectures for 2-D DCT and IDCT processors not only simplify hardware but also reduce the power consumption with high performances.  ...  The VLSI chip implementations of DCT for real-time applications can be found in [1]- [8] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/pdcat.2006.70">doi:10.1109/pdcat.2006.70</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/pdcat/SungSYH06b.html">dblp:conf/pdcat/SungSYH06b</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/jigriehcazhmhfl3stpifrocty">fatcat:jigriehcazhmhfl3stpifrocty</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200318115242/http://www.wseas.us/e-library/conferences/2007hangzhou/papers/560-118.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ae/8d/ae8d8094c88868df9453f0042d0169f45f49d944.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/pdcat.2006.70"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Pipeline architecture for DCT/IDCT

J. Nikara, J. Takola, D. Akopian, J. Saarinen
<i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/kucxvipvevedfgtsl3pnvxorse" style="color: black;">ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)</a> </i> &nbsp;
In this paper, a unified sequential architecture for 8-point discrete cosine transform and its inverse is described.  ...  The architecture is based on rescheduled constant geometry algorithms, which are mapped onto a one-dimensional structure with the aid of vertical projection.  ...  I are regular, thus they lend themselves well to VLSI implementations. Therefore, the constant geometry algorithm is a good starting point for developing parallel architectures for DCT and IDCT.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iscas.2001.922384">doi:10.1109/iscas.2001.922384</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/iscas/NikaraTAS01.html">dblp:conf/iscas/NikaraTAS01</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/yewpbes3lrbo7kxdoxhtfjdeyu">fatcat:yewpbes3lrbo7kxdoxhtfjdeyu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190226134752/http://pdfs.semanticscholar.org/7f5c/0165f81166edf2dde022ee8305c06f60c66c.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/7f/5c/7f5c0165f81166edf2dde022ee8305c06f60c66c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iscas.2001.922384"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Algorithm-based low-power transform coding architectures: the multirate approach

An-Yeu Wu, K.J. Ray Liu
<span title="">1998</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
Then the multirate low-power design is extended to the modulated lapped transform (MLT), extended lapped transform (ELT), and a unified low-power transform coding architecture.  ...  Finally, we perform finite-precision analysis for the multirate DCT architectures.  ...  This makes the proposed architectures very suitable for VLSI implementations.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/92.736144">doi:10.1109/92.736144</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/bghkt2woezctlewhpjqgko4eui">fatcat:bghkt2woezctlewhpjqgko4eui</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170829055753/http://sig.umd.edu/publications/wu_VLSI_199812.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/5e/e0/5ee09fd7d6629109b68a0bd61a7848faa5c5ec7b.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/92.736144"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

Hong Liang, He Weifeng, Zhu Hui, Mao Zhigang
<span title="">2013</span> <i title="Institute of Electronics, Information and Communications Engineers (IEICE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fvf4s3u4inbjpnfv6imirwcvam" style="color: black;">IEICE Electronics Express</a> </i> &nbsp;
In this paper, a full pipelined 2-D IDCT/IDST VLSI architecture compatible with HEVC standard is presented for the first time.  ...  In consequence, it offers a costeffective solution for the future UHDTV applications.  ...  Shen presented a unified 4/8/16/32-point integer IDCT architecture for HEVC standard [8] . All in all, all these architectures are focused on DCT/IDCT VLSI design for the developing HEVC standard.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.10.20130210">doi:10.1587/elex.10.20130210</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/genkiz3id5flvphc2celi63c2a">fatcat:genkiz3id5flvphc2celi63c2a</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180727162224/https://www.jstage.jst.go.jp/article/elex/10/9/10_10.20130210/_pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ad/fd/adfdaf1df703b0b12409ff2b34f31363ada1aabd.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.10.20130210"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Unified array architecture for discrete cosine transform, sine transform and their inverses

Jiun-In Guo, Chein-Wei Jen, Chingson Chen
<span title="1995-10-12">1995</span> <i title="Institution of Engineering and Technology (IET)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5njumqonprdi3jwzrhnh22m7pm" style="color: black;">Electronics Letters</a> </i> &nbsp;
The features of high throughput performance and low areatime complexity make the proposed array useful for very high speed applications.  ...  It is also worth noting that the design for the I-D IDCT can be directly applied to evaluate the 2-D IDCT based on row-column decomposition.  ...  Moreover, the design in [8] should entail much hardware cost in VLSI implementation for the recursive generation of the transform kernels.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1049/el:19951254">doi:10.1049/el:19951254</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6a6lt4tgy5hohh23nn2g5akp5a">fatcat:6a6lt4tgy5hohh23nn2g5akp5a</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810143153/https://ir.nctu.edu.tw/bitstream/11536/1700/1/A1995TA92000013.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a3/c1/a3c1302d0cb94055ca3abeef4129ab440db4bd85.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1049/el:19951254"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

A serial-parallel architecture for two-dimensional discrete cosine and inverse discrete cosine transforms

Hyesook Lim, V. Piuri, E.E. Swartzlander
<span title="">2000</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5jlmyrayyrdazh5awdlsoec77q" style="color: black;">IEEE transactions on computers</a> </i> &nbsp;
This paper presents the architecture of an efficient implementation of a two-dimensional DCT/IDCT transform processor via a serial-parallel systolic array that does not require transposition.  ...  A popular approach for implementing the 2D DCT/IDCT is the row-column decomposition method [3] , [4] , in which the 2D transform is computed by applying the 1D DCT/IDCT by rows and, then, by columns.  ...  serial-parallel architecture implementing the DCT/IDCT array processor introduced in Section 2 is shown in Fig. 4 .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/12.895848">doi:10.1109/12.895848</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mfvcq5pmvzep7g2y5zmi7zon7q">fatcat:mfvcq5pmvzep7g2y5zmi7zon7q</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170517023337/http://piurilabs.di.unimi.it:80/Papers/tc_2000.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/89/b7/89b73fb089bede3b96b862d13f4b2f2947668f75.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/12.895848"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Low-power architectures for compressed domain video coding co-processor

Jie Chen, K.J. Ray Liu
<span title="">2000</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/sbzicoknnzc3tjljn7ifvwpooi" style="color: black;">IEEE transactions on multimedia</a> </i> &nbsp;
Low power as a de facto is one of the most important criteria for many signal-processing system designs, particularly in multimedia cellular applications and multimedia system on chip design.  ...  We demonstrate both low-power and high-speed can be accomplished at algorithm/architecture level.  ...  Two-stage look-ahead type-II DCT/IDCT coder, the switch setting is for DCT and the complementary setting is for inverse IDCT computation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/6046.845015">doi:10.1109/6046.845015</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/4w7boolugvex7kordyhqksdnwq">fatcat:4w7boolugvex7kordyhqksdnwq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809063003/http://www.vtvt.ece.vt.edu/research/references/video/DCT_Video_Compression/Chen00a.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f0/b8/f0b86f8821f22033c99101bf0173e7c0f7403744.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/6046.845015"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding

Hong Liang, He Weifeng, He Guanghui, Mao Zhigang
<span title="">2016</span> <i title="Institute of Electronics, Information and Communications Engineers (IEICE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fvf4s3u4inbjpnfv6imirwcvam" style="color: black;">IEICE Electronics Express</a> </i> &nbsp;
Consequently, the proposed architecture offers a cost-efficient solution for future UHD applications.  ...  In this paper, a novel area-efficient IDCT/IDST architecture for Ultra-High Definition (UHD) video applications is proposed.  ...  Chiang [5] et al. proposed a reconfigurable inverse transform architecture for HEVC 4K Â 2K video decoding in 2013. To support the DCT/IDCT and the Hadamard transform, J.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.13.20160019">doi:10.1587/elex.13.20160019</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/te7x2y4zajhuhiizlvwimj4uji">fatcat:te7x2y4zajhuhiizlvwimj4uji</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180726211804/https://www.jstage.jst.go.jp/article/elex/13/6/13_13.20160019/_pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/94/07/940787f4d5385592f89231b94be98e9e4b2eb26f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.13.20160019"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Algorithm-based low-power and high-performance multimedia signal processing

K.J. Ray Liu, An-Yeu Wu, A. Raghupathy, Jie Chen
<span title="">1998</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yfvtieuumfamvmjlc255uckdlm" style="color: black;">Proceedings of the IEEE</a> </i> &nbsp;
Such an architecture forms a new generation of high-performance embedded signal processor based on the adaptive computing model.  ...  A digital-signal-processing engine that is an adaptive reconfigurable architecture is also derived from the common features of our approach.  ...  ., the MPEG audio codec in which a 32-point DCT/IDCT is used [64] ).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/5.687834">doi:10.1109/5.687834</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/s7ujyq5ovncsnejzocdcsylqde">fatcat:s7ujyq5ovncsnejzocdcsylqde</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808191202/http://sig.umd.edu/publications/liu_IEEEproc_199806.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/d9/71/d9710355a6d97b45c57fc80b4c266b6f8bab2154.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/5.687834"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Efficient architecture and design of an embedded video coding engine

J. Chen, K.J. Ray Liu
<span title="">2001</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/sbzicoknnzc3tjljn7ifvwpooi" style="color: black;">IEEE transactions on multimedia</a> </i> &nbsp;
Therefore, in this paper, we propose a novel COordinate Rotation Digital Computer (CORDIC) architecture for combined design of discrete cosine transform (DCT) and half-pel motion estimation.  ...  Furthermore, we implement the embedded design on a dedicated single chip to demonstrate its performance.  ...  VLSI DESIGN FOR EMBEDDED VIDEO CODING ENGINE The regular, modular, and locally connected architecture of our design is suitable for VLSI implementation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/6046.944473">doi:10.1109/6046.944473</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/cw4oemcytjfsnhotwa3pnjurqu">fatcat:cw4oemcytjfsnhotwa3pnjurqu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808080401/http://sig.umd.edu/publications/chen_TM_200109.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/48/8b/488b19a50bf5d6ef4ac6d77f2a7ecddd6e123d42.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/6046.944473"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Algorithm-based low-power transform coding architectures

An-Yeu Wu, K.J. Ray Liu Liu
<span title="">1995</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rc5jnc4ldvhs3dswicq5wk3vsq" style="color: black;">1995 International Conference on Acoustics, Speech, and Signal Processing</a> </i> &nbsp;
The resulting multirate lowpower architectures are regular, modular, and free of global communications. Such properties are very suitable for VLSI implementations.  ...  The proposed architectures can also be applied to very high-speed block transforms where only lowspeed operators are required.  ...  Table 1 : 1 Parameter setting for the unified low-power IIFt transform module. Table 2 : 2 Comparison of hardware cost for the DCT, IDCT, MLT, and ELT with their low-power designs.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/icassp.1995.479582">doi:10.1109/icassp.1995.479582</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/icassp/WuL95.html">dblp:conf/icassp/WuL95</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/b7hg7w2fs5dx3kapy4of5yv524">fatcat:b7hg7w2fs5dx3kapy4of5yv524</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20131229150105/http://sig.umd.edu/publications/Wu_1995_ICASSP.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/74/ec/74ec79a05b2c98f7581a1a5774e7f178cdfe7f7e.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/icassp.1995.479582"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>
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