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A tutorial on logic synthesis for lookup-table based FPGAs

Francis
1992 IEEE/ACM International Conference on Computer-Aided Design  
One important class of FPGAs are those that use lookup tables (L UTs) to implement combinational logic.  ...  The ability of a K-input LUT to implement any Boolean function of Ii-variables di$eren,tiates the synthesis of LUT circuits from synthesis for conventional ASIC technologies.  ...  This tutorial discusses combinational logic synthesis for FPGAs that use lookup tables (LUTs) to implement combinational logic, and focuses on issues that differentiate LUT synthesis from conventional  ... 
doi:10.1109/iccad.1992.279399 dblp:conf/iccad/Francis92 fatcat:lrb3epjrzzarzoffs2bmivbukm

FPGA Design Automation: A Survey

Deming Chen, Jason Cong, Peichen Pan
2006 Foundations and Trends® in Electronic Design Automation  
We focus on the LUT-based FPGA architecture in which the BLE consists of one k-input lookup table (k-LUT) and one flip-flop. The output of the k-LUT can be either registered or un-registered.  ...  For example, when FPGAs were first debuted in the mid-to late-80s, the Xilinx XC2064 FPGA had only 64 lookup tables (LUTs) and it was used as simple glue logic.  ... 
doi:10.1561/1000000003 fatcat:pops4k5ddrhvdgklbw2wa2ls4i

Hands-on with the NetFPGA to build a Gigabit-rate Router

Nick McKeown, John W. Lockwood, Jad Naous, Glen Gibb, Adam Covington
2007 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007)  
The platform can be used by researchers to prototype advanced services for next-generation networks. 15th IEEE Symposium on High-Performance Interconnects Unrecognized Copyright Information  ...  He has been working on the NetFPGA since 2006, and has recently developed the base router and switch designs on the NetFPGA as well as a high precision event capture system for monitoring queue occupancies  ...  He has been working on the NetFPGA platform since 2004 and was the lead designer for the current hardware version.  ... 
doi:10.1109/hoti.2007.4296800 fatcat:p2fgqiiy3vfg5msrk4xivwhs7i

Hands-on with the NetFPGA to build a Gigabit-rate Router

Nick McKeown, John W. Lockwood, Jad Naous, Glen Gibb, Adam Covington
2007 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007)  
The platform can be used by researchers to prototype advanced services for next-generation networks. 15th IEEE Symposium on High-Performance Interconnects Unrecognized Copyright Information  ...  He has been working on the NetFPGA since 2006, and has recently developed the base router and switch designs on the NetFPGA as well as a high precision event capture system for monitoring queue occupancies  ...  He has been working on the NetFPGA platform since 2004 and was the lead designer for the current hardware version.  ... 
doi:10.1109/hoti.2007.18 dblp:conf/hoti/McKeownLNGC07 fatcat:vfz2csf6xbg4rccpgcngfqeqaa

Rapid Development of Gzip with MaxJ [chapter]

Nils Voss, Tobias Becker, Oskar Mencer, Georgi Gaydadjiev
2017 Lecture Notes in Computer Science  
Next we show on the example of our gzip implementation how an engineer without previous MaxJ experience can quickly develop and optimize a real, complex application.  ...  Recent advances in high-level synthesis have brought forward tools that relieve the burden of FPGA application development but the achieved performance results can not approximate designs made using low-level  ...  The hash table lookup provides n 2 possible matches, since we perform n lookups for each input byte.  ... 
doi:10.1007/978-3-319-56258-2_6 fatcat:phzebnbpc5fcvl7l6mzjkzs5h4

A Framework for Teaching Real-Time Digital Signal Processing With Field-Programmable Gate Arrays

T.S. Hall, D.V. Anderson
2005 IEEE Transactions on Education  
The synthesized hardware is implemented on field-programmable gate arrays (FPGAs), which provide a fast and cost-effective way of prototyping hardware systems in a laboratory environment.  ...  This framework allows students to expand their previous knowledge into a more complete understanding of the entire design process from specification and simulation through synthesis and verification.  ...  Topics covered include basic FPGA concepts and architectures, introduction to VHDL for synthesis, and a review of state machine design with an emphasis on VHDL implementations.  ... 
doi:10.1109/te.2005.853069 fatcat:v4keyxvtjrba5fsxokyolzzn7e

High-Level Design Tools for Floating Point FPGAs

Deshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski
2015 Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '15  
Table 4 shows the implementation results for this benchmark on Stratix V using soft logic and Arria 10 Table 5.  ...  A implemented a particular one described in [5] for 4K-point FFT similar implementation is used for the real part of the on an Altera Stratix V FPGA.  ... 
doi:10.1145/2684746.2689079 dblp:conf/fpga/SinghPC15 fatcat:xk2qbx244fczffdbycnfaaedv4

Measuring the Gap Between FPGAs and ASICs

Ian Kuon, Jonathan Rose
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption.  ...  implement them in FPGAs and ASICs is on average 40.  ...  If we consider such a design, only the lookup tables and flip-flops perform the basic logic operations that would also be necessary in a standard cell design.  ... 
doi:10.1109/tcad.2006.884574 fatcat:zdrfooiaffh5zjevroqcni7gs4

Measuring the gap between FPGAs and ASICs

Ian Kuon, Jonathan Rose
2006 Proceedings of the internation symposium on Field programmable gate arrays - FPGA'06  
This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption.  ...  implement them in FPGAs and ASICs is on average 40.  ...  ACKNOWLEDGEMENTS We are indebted to Jaro Pristupa for the extensive support he provided for both the technology kits and the numerous CAD tools required for this work.  ... 
doi:10.1145/1117201.1117205 dblp:conf/fpga/KuonR06 fatcat:35r7w6uyxjhvnm44geleloc6gy

Isolation mechanisms for high-speed packet-processing pipelines [article]

Tao Wang, Xiangrui Yang, Gianni Antichi, Anirudh Sivaraman, Aurojit Panda
2022 arXiv   pre-print
Finally, we demonstrate that feasibility of implementing Menshen on ASICs by using the FreePDK45nm technology library and the Synopsys DC synthesis software, showing that our design meets timing at a 1GHz  ...  We have prototyped Menshen on two FPGA platforms (NetFPGA and Corundum). We show that our design provides isolation, and allows new modules to be loaded without impacting the ones already running.  ...  We also thank Mike Walfish, Ravi Netravali, Mina Tahmasbi Arashloo, Amy Ousterhout, and Fabian Ruffy for their suggestions on this paper.  ... 
arXiv:2101.12691v4 fatcat:als2ow34ujej7pmw3tnkttcf7q

The P4->NetFPGA Workflow for Line-Rate Packet Processing

Stephen Ibanez, Gordon Brebner, Nick McKeown, Noa Zilberman
2019 Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '19  
Our target is the NetFPGA SUME platform, a 4 × 10 Gb/s PCIe card designed for use in universities for teaching and research.  ...  The goal of the work presented here is to make it easier for engineers, researchers and students to learn how to program using P4, and to build prototypes running on real hardware.  ...  Furthermore, we acknowledge the Xilinx University Program (XUP) for its continued support of the NetFPGA project.  ... 
doi:10.1145/3289602.3293924 dblp:conf/fpga/IbanezBMZ19 fatcat:omtgx3kkt5e47ng2bvpy6j6rhy

Hardware-Based Runtime Verification with Embedded Tracing Units and Stream Processing [chapter]

Lukas Convent, Sebastian Hungerecker, Torben Scheffel, Malte Schmitz, Daniel Thoma, Alexander Weiss
2018 Lecture Notes in Computer Science  
In this tutorial, we present a comprehensive approach to nonintrusive monitoring of multi-core processors.  ...  real time using FPGAs.  ...  direct jumps and can store those in a lookup table in the memory of the FPGA.  ... 
doi:10.1007/978-3-030-03769-7_5 fatcat:bxgfjsyzpfbpfksid3gu54kfxq

Programmable logic devices in experimental quantum optics

John Stockton, Michael Armen, Hideo Mabuchi
2002 Journal of the Optical Society of America. B, Optical physics  
As a tutorial illustration of the PLD implementation process, a field programmable gate array (FPGA) controller is used to stabilize the output of a Fabry-Perot cavity.  ...  We discuss the unique capabilities of programmable logic devices (PLD's) for experimental quantum optics and describe basic procedures of design and implementation.  ...  Lookup Tables Most FPGA chips come equipped with large blocks of internal RAM that can be used as generalized functions or lookup tables (LUT).  ... 
doi:10.1364/josab.19.003019 fatcat:khnfw7fduvffvkdgqoxgf4jexi

System level design and verification using a synchronous language

G. Berry, M. Kishinevsky, S. Singh
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
The tutorial will demonstrate what the synchronous language offers for the modeling, design, analysis and implementation of systems that comprise hardware and software. It will be based on Esterel.  ...  Esterel models have proved to be useful for rapid design space exploration and verification at system level, without resorting to detailed implementation and slow bit-level event-based simulation.  ...  The basic implementation uses 111 look-up tables (a lookup table can implement any four input one output combinational function) and 92 flip-flops and operates at a maximum frequency of 125MHz on the XC2V1000  ... 
doi:10.1109/iccad.2003.159720 fatcat:7sidxprs4zgfffv7h5e6rdix74

A Hardware-in-the-Loop Platform for DC Protection

Mark Vygoder, Matthew Milton, Jacob Gudex, Robert Cuzner, Andrea Benigni
2020 IEEE Journal of Emerging and Selected Topics in Power Electronics  
The approach combines using Latency Based Linear Multistep Compound (LB-LMC), a real-time simulation method for power electronic, and National Instruments (NI) FPGA hardware to enable dc protection design  ...  I would like to thank my family on the east coast for their support.  ...  All vi's and subvi's shown in this chapter were made by the author. 6 lookup tables were implemented, one for each of the angles required for the dq transform; however, these lookup tables are not able  ... 
doi:10.1109/jestpe.2020.3017769 fatcat:6d4fookm4ngr3dzyksqfdc56ge
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