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A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008 2008 IEEE International Symposium on Circuits and Systems  

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This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder.  ...  It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 × 1080 pixels at 30 fps which haven't been realized by conventional methods[1][2].  ...  We designed a sub 100-mW H.264/AVC main profile motion estimation processor core for MBAFF encoding. 16 × 16, 16 × 8, 8 × 16, and 8 × 8 block sizes are supported for an HDTV resolution video (1920 × 1080  ... 
doi:10.1109/iscas.2008.4541551 dblp:conf/iscas/MurachiMMHIIYLKKY08 fatcat:amjzntjg6vhqzigrknv7z32hea
Citation

Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto. "A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding." 2008 IEEE International Symposium on Circuits and Systems (2008) 848-851