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A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory

Matheus Schuh, Claire Maiza, Joel Goossens, Pascal Raymond, Benoit Dupont de Dinechin
2020 2020 IEEE Real-Time Systems Symposium (RTSS)  
A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory. 2020 IEEE Real-Time Systems Symposium (RTSS), Abstract-We  ...  models with and without isolation, and finally (iii) guidelines for predictable implementation of a data-flow application on multi-core processors with shared on-chip memory.  ...  Acknowledgment This work was performed in the scope of the ES3CAP research project, under the Bpifrance Invest for the Future Program (Programme d'Investissements d'Avenir -PIA).  ... 
doi:10.1109/rtss49844.2020.00034 fatcat:72fpqlkk5zgsbiqfkjixbem3f4

Parallel code generation of synchronous programs for a many-core architecture

Amaury Graillat, Matthieu Moy, Pascal Raymond, Benoit Dupont de Dinechin
2018 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
Implementation of such programs on a many-core architecture must ensure a bounded response time and preserve the functional behavior by taking interference into account.  ...  Data-flow Synchronous languages such as Lustre or Scade are widely used for avionic critical software. Programs are described by networks of computational nodes.  ...  ACKNOWLEDGMENT Many thanks to Mustapha Lo (Airbus Helicopter/Verimag) who provided the idea and structure of the "sensor processing" case-study.  ... 
doi:10.23919/date.2018.8342182 dblp:conf/date/GraillatMRD18 fatcat:byutr534pzakpj6ixbvsyiakxi

T-CREST: Time-predictable multi-core architecture for embedded systems

Martin Schoeberl, Sahar Abbaspour, Benny Akesson, Neil Audsley, Raffaele Capasso, Jamie Garside, Kees Goossens, Sven Goossens, Scott Hansen, Reinhold Heckmann, Stefan Hepp, Benedikt Huber (+11 others)
2015 Journal of systems architecture  
With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7.  ...  Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time.  ...  Acknowledgment This work was partially funded by the European Union's 7th Framework Programme under grant agreement No. 288008: Time-predictable Multi-Core Architecture for Embedded Systems  ... 
doi:10.1016/j.sysarc.2015.04.002 fatcat:yts4coszkbg7vbes3b4hzdyzui

Reconciling performance and predictability on a many-core through off-line mapping

Thomas Carle, Manel Djemal, Daniela Genius, Francois Pecheux, Dumitru Potop Butucaru, Robert de Simone, Franck Wajsburt, Zhen Zhang
2014 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
In particular, its distributed shared memory programming model allows the use of a code generation flow based on the (unmodified) gcc compiler chain.  ...  We conclude our paper with a presentation of some ongoing work on the subject: A case study (an implementation of the H.264 decoder) meant to test the limitations of our method.  ...  Our ongoing work on H.264 shows that for some of these algorithms it is possible to put them in a data-flow form facilitating predictable implementation.  ... 
doi:10.1109/recosoc.2014.6861367 dblp:conf/recosoc/CarleDGPPSWZ14 fatcat:mbxqa25um5hzviyd6ythe4id74

Exploring architectural heterogeneity in intelligent vision systems

Nanchini Chandramoorthy, Giuseppe Tagliavini, Kevin Irick, Antonio Pullini, Siddharth Advani, Sulaiman Al Habsi, Matthew Cotter, John Sampson, Vijaykrishnan Narayanan, Luca Benini
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
Using this platform, we illustrate data flow and control processing optimizations that provide for performance gains similar to custom ASICs for a wide range of vision benchmarks. 1 978-1-4799-8930-0/15  ...  Limited power budgets and the need for high performance computing have led to platform customization with a number of accelerators integrated with CMPs.  ...  NSF and funded by Nano-Tera.ch with Swiss Confederation financing and infrastructure supported by NSF award 1205618.  ... 
doi:10.1109/hpca.2015.7056017 dblp:conf/hpca/ChandramoorthyT15 fatcat:bxpktq7phze6vdgzh7vzl7e42y

Challenges in Future Avionic Systems on Multi-Core Platforms

Andreas Lofwenmark, Simin Nadjm-Tehrani
2014 2014 IEEE International Symposium on Software Reliability Engineering Workshops  
Moreover, there is a departure from today's single core computing, and we need to address the problem of how to guarantee determinism (in time and space) for application tasks running on multiple cores  ...  and interacting through shared memory.  ...  Cache sharing is present on platforms where the cores share one or more levels of cache. Cache coherence is needed for keeping shared data consistent among the core local caches and the main memory.  ... 
doi:10.1109/issrew.2014.70 dblp:conf/issre/LofwenmarkN14 fatcat:2utl3yblnjenboqyjfebblaaba

A Survey of Techniques for Reducing Interference in Real-time Applications on Multicore Platforms

Tamara Lugo, Santiago Lozano, Javier Fernandez, Jesus Carretero
2022 IEEE Access  
It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis.  ...  This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020.  ...  The model implements dedicated and shared bank partitions, splits DRAM banks, and implements a task allocation algorithm that allocates intensive memory tasks on the same core with dedicated DRAM banks  ... 
doi:10.1109/access.2022.3151891 fatcat:vutgetjua5byxczcivmw2esqtq

Efficient Contention-Aware Scheduling of SDF Graphs on Shared Multi-Bank Memory

Hai Nam Tran, Alexandre Honorat, Jean-Pierre Talpin, Thierry Gautier, Loic Besnard
2019 2019 24th International Conference on Engineering of Complex Computer Systems (ICECCS)  
In this article, we present a scheduling analysis technique that exploits a shared multi-bank memory architecture to efficiently schedule parallel real-time applications modeled as synchronous data flow  ...  Novel memory architectures have been introduced in multi/many-core processors to address the performance bottle neck due to shared memory accesses.  ...  Resource-Sharing Platform Model We study the shared multi-bank memory introduced in [8] . This particular architecture already exists in industrial platforms such as the Kalray MPPA [9] .  ... 
doi:10.1109/iceccs.2019.00020 dblp:conf/iceccs/TranHTGB19 fatcat:lbycamkdevaczdiw7f3lltdgie

Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities [article]

Mahya Morid Ahmadi, Faiq Khalid, Muhammad Shafique
2021 arXiv   pre-print
In this paper, we present a brief yet comprehensive study of the security vulnerabilities in modern microprocessors with respect to side-channel attacks and their respective mitigation techniques.  ...  Towards this, we perform an in-depth analysis of the applicability and practical implications of cache attacks on RISC-V microprocessors and their associated challenges.  ...  ACKNOWLEDGMENT This work was partially supported by Doctoral College Resilient Embedded Systems which is run jointly by TU Wien's Faculty of Informatics and FH-Technikum Wien.  ... 
arXiv:2106.08877v1 fatcat:zdalqpzvajatjhvu4ik7ccvwky

Temporal Isolation of Hard Real-Time Applications on Many-Core Processors

Quentin Perret, Pascal Maurere, Eric Noulard, Claire Pagetti, Pascal Sainrat, Benoit Triquet
2016 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)  
We tested the correctness of the approach through a series of benchmarks and the implementation of a case study.  ...  In order to partially address those issues, we propose an appropriate execution model, that restricts the applications behaviours, which has been implemented on the KALRAY MPPA R -256.  ...  Once an application has been implemented following the work-flow, it is predictable in the sense that it behaves temporally exactly the same whether it runs alone on the platform or with other applications  ... 
doi:10.1109/rtas.2016.7461363 dblp:conf/rtas/PerretMNPST16 fatcat:noy6uyamv5cwzmyixmln5mj4ne

Designing Application-Specific Heterogeneous Architectures from Performance Models

Thanh Cong, Francois Charot
2019 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)  
An application-specific program is profiled by the dynamic execution trace and is used to construct a data flow model of the accelerator.  ...  In this paper, we propose an approach for designing application-specific heterogeneous systems based on performance models through combining accelerator and processor core models.  ...  ACKNOWLEDGMENTS The authors would like to thank Bluespec for providing us the Bluespec tools and also Intel Labs for giving us access to a cluster of the integrated BDW/FPGAs, within IL's vLab academic  ... 
doi:10.1109/mcsoc.2019.00045 dblp:conf/mcsoc/CongC19 fatcat:nxpx56t2yna7rhpev4qhutu6ei

The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores

Igor Loi, Alessandro Capotondi, Davide Rossi, Andrea Marongiu, Luca Benini
2018 IEEE Transactions on Multi-Scale Computing Systems  
Exploiting the instruction locality typical of data-parallel applications, we explore two different shared instruction cache architectures, based on energy-efficient latch-based memory banks: one leveraging  ...  The results show that the shared cache architectures are able to efficiently execute a much wider set of applications (including those featuring large memory footprint and irregular access patterns) with  ...  We thus studied two different cluster architectures based on shared instruction caches: one featuring a crossbar between the processors and the memory banks, and one exploiting memory banks with multiple  ... 
doi:10.1109/tmscs.2017.2769046 fatcat:ta644xddx5b7hjmoqsipow2aiy

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

Claire Maiza, Hamza Rihani, Juan M. Rivas, Joël Goossens, Sebastian Altmeyer, Robert I. Davis
2019 ACM Computing Surveys  
This survey provides an overview of the scientiic literature on timing veriication techniques for multi-core real-time systems.  ...  The survey highlights the key issues involved in providing guarantees of timing correctness for multi-core systems.  ...  EPSRC Research Data Management: No new primary data was created during this study  ... 
doi:10.1145/3323212 fatcat:mn6xmduiyjfgzhemn5s2lmfgje

Performance efficiency of context-flow system-on-chip platform

R. Beidas, Jianwen Zhu
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective programming model, while not  ...  We demonstrate the performance efficiency of this architecture over bus based and packet-switch based networks by two case studies using a multi-processor architecture simulator.  ...  and simulated on the multi-processor context-flow architecture platform.  ... 
doi:10.1109/iccad.2003.159711 fatcat:fksjka24dzed7db225wv3mw33y

SPHERE: A Multi-SoC Architecture for Next-generation Cyber-Physical Systems Based on Heterogeneous Platforms

Alessandro Biondi, Daniel Casini, Giorgiomaria Cicero, Niccolo Borgioli, Giorgio Buttazzo, Gaetano Patti, Luca Leonardi, Lucia Lo Bello, Marco Solieri, Paolo Burgio, Ignacio Sanudo, Angelo Ruocco (+5 others)
2021 IEEE Access  
They include isolation mechanisms for mixed-criticality applications, predictable I/O virtualization, the management of time-sensitive networks with heterogeneous traffic flows, and the management of field-programmable  ...  The main challenges addressed by SPHERE are discussed in the paper along with a set of new technologies developed in the context of the project.  ...  ACKNOWLEDGMENT This work has been partially supported by the Italian Ministry of University and Research (MIUR), under the SPHERE project funded within the PRIN-2017 framework (grant no. 93008800505).  ... 
doi:10.1109/access.2021.3080842 fatcat:kxhfuoc7zzdediivmah7tyl5ea
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