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A small and adaptive coprocessor for information flow tracking in ARM SoCs [article]

Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas, Vianney Lapôtre, Guy Gogniat
2018 arXiv   pre-print
DIFT (Dynamic Information Flow Tracking) has been a hot topic for more than a decade.  ...  These goals are accomplished by taking advantage of a notable feature of ARM CoreSight components (context ID) combined with a custom DIFT coprocessor and RFBlare.  ...  In other words, the DIFT coprocessor can determine, thanks to the context ID feature, the thread executed on the ARM CPU and can propagate tags for the corresponding information flows.  ... 
arXiv:1812.01541v1 fatcat:re7vqhee7zc7vh5u3mziw5f67a

A small and adaptive coprocessor for information flow tracking in ARM SoCs

Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas, Vianney LapOtre, Guy Gogniat
2018 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)  
DIFT (Dynamic Information Flow Tracking) has been a hot topic for more than a decade.  ...  These goals are accomplished by taking advantage of a notable feature of ARM CoreSight components (context ID) combined with a custom DIFT coprocessor and RFBlare.  ...  In other words, the DIFT coprocessor can determine, thanks to the context ID feature, the thread executed on the ARM CPU and can propagate tags for the corresponding information flows.  ... 
doi:10.1109/reconfig.2018.8641695 dblp:conf/reconfig/WahabCAHBLG18 fatcat:zx5elrvskjblhfho6mj3jpk4we

Dynamic Information Flow Tracking: Taxonomy, Challenges, and Opportunities

Kejun Chen, Xiaolong Guo, Qingxu Deng, Yier Jin
2021 Micromachines  
Dynamic information flow tracking (DIFT) has been proven an effective technique to track data usage; prevent control data attacks and non-control data attacks at runtime; and analyze program performance  ...  Therefore, a series of DIFT techniques have been developed recently. In this paper, we summarize the current DIFT solutions and analyze the features and limitations of these solutions.  ...  The DIFT engine in the processor and coprocessor can serve as a management unit for information flow in the whole SoC. Future Research Software and hardware co-design is a good future direction.  ... 
doi:10.3390/mi12080898 fatcat:zfkiddrjvbfjli7ht6x5jgyp7q

Design, synthesis and verification of a smart imaging core using SystemC

Wido Kruijtzer, Victor Reyes, Winfried Gehrke
2005 Design automation for embedded systems  
The smart imaging core integrates an ARM processor and two specific hardware blocks for image processing: a smart imaging coprocessor and a motion estimation coprocessor.  ...  In this paper the development of a smart imaging core following a SystemC-based design flow is presented.  ...  This work was partly sponsored by the European Commission in the IST-2001-34410 CAMELLIA project.  ... 
doi:10.1007/s10617-006-0069-7 fatcat:77ro2kkrdfcgxf4hjf76ppq6cu

A system on chip-based real-time tracking system for amphibious spherical robots

Shuxiang Guo, Shaowu Pan, Xiaoqiong Li, Liwei Shi, Pengyi Zhang, Ping Guo, Yanlin He
2017 International Journal of Advanced Robotic Systems  
Moreover, dynamic reconfiguration was used to switch accelerators online for reducing resource consumption and improving system adaptability.  ...  Aiming at vision applications of our amphibious spherical robot, a real-time detection and tracking system adopting Gaussian background model and compressive tracking algorithm was designed and implemented  ...  Funding The author(s) disclosed receipt of the following financial support for the research, authorship and/or publication of this article: This work was supported by National Natural Science  ... 
doi:10.1177/1729881417716559 fatcat:mezol6kpxrfkvcwb3jcwwnujqy

Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384,512) for Hardware Implementations [chapter]

Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
2007 Lecture Notes in Computer Science  
For example, DMA improves the interfaces between memory and a coprocessor in a SOC system.  ...  The secret vault is a small memory that is used to store keys and other sensitive information that will be used by security coprocessors in the system.  ... 
doi:10.1007/978-3-540-77535-5_8 fatcat:nv436nlyf5dkzmxxuna66r33lq

Real-time visual tracking system modelling in MPSoC using platform based design

Zai Jian Jia, Tomás Bautista, Antonio Núñez, Cayetano Guerra, Mario Hernández, Matthias F. Carlsohn, Nasser Kehtarnavaz
2009 Real-Time Image and Video Processing 2009  
In our current work, a visual tracking system with real-time behaviour (25 frames/sec) is used like a reference application, and also, guidelines for our future CVS applications development.  ...  platform, and this way, a solution for a set of applications using the same architecture is offered and not just for one application.  ...  ACKNOWLEDGEMENT This research is funded by the Spanish Ministry for Science and Technology, grant AP2006-02986, and Spanish Ministry for Science and Innovation, grant TEC2006-13599-C02.  ... 
doi:10.1117/12.811332 dblp:conf/rivp/JiaBNGH09 fatcat:u5is336ftnc7naqjfxfnl3mplq

An FPGA Kalman-MPPT implementation adapted in SST-based Dual Active Bridge Converters for DC Microgrids Systems

Guillermo Becerra-Nunez, Alejandro Castillo-Atoche, Javier Vazquez-Castillo, Asim Datta, Renan Quijano-Cetina, Rafael Pena-Alzola, Roberto Carrasco-Alvarez, Edith Osorio-De-La-Rosa
2020 IEEE Access  
For example, a time-area performance analysis in FPGAS of an adaptive perturb and observe (P&O) maximum power point tracking controller for photovoltaic application is presented in [15] .  ...  In the experiment, the Kalman-MPPT is employed as hardware coprocessor and the Cortex-A9 ARM processor is used for the DAB-SST closed-loop controller.  ...  He is a professor at the Universidad Autónoma de Yucatán and at the Instituto Tecnológico de Mérida.  ... 
doi:10.1109/access.2020.3033718 fatcat:jfusiyju5vavpi7jac5qaw7b54

Survey On Moving Object Tracking And Detection

DHANASHRI V. MADHEKAR, PROF. MRINAL R. BACHUTE
2017 Zenodo  
To identify and tracking the real time object is important concept in computer vision. In the paper, image processing algorithms are used for tracking a moving video object.  ...  Object tracking is an important component of many computer vision systems. It is widely used in number of fields such as video surveillance, robotics, medical imaging, and human computer interface.  ...  Moving Object Detection and Tracking Based on ZYNQ FPGA and ARM SOC by Wenchao Liu [4] In the paper, FPGA-based moving object detection and tracking system is introduced for image processing application  ... 
doi:10.5281/zenodo.1446016 fatcat:nzs7oeugnbgothu5th6ehkov3i

Cache-Coherent Heterogeneous Multiprocessing as Basis for Streaming Applications [chapter]

Jos van Eijndhoven, Jan Hoogerbrugge, M.N. Jayram, Paul Stravers, Andrei Terechko
2005 Philips Research  
These chips will support the execution of a mix of concurrent applications that are not known in detail at chip design time.  ...  and memory hierarchies.  ...  (For more information, see the section "Memory Coherence in Shared Memory Multiprocessors" in [Fly1995].)  ... 
doi:10.1007/1-4020-3454-7_3 fatcat:f65fpatwlrdipi27dc3ongnxze

A Scalable FPGA-based Architecture for Depth Estimation in SLAM [article]

Konstantinos Boikos, Christos-Savvas Bouganis
2019 arXiv   pre-print
Meanwhile, research in this field has provided many advances for information rich processing and semantic understanding, combined with high computational requirements for real-time processing.  ...  This work provides a solution to bridging this gap, in the form of a scalable SLAM-specific architecture for depth estimation for direct semi-dense SLAM.  ...  Acknowledgments The support of the EPSRC Centre for Doctoral Training in High Performance Embedded and Distributed Systems (HiPEDS, Grant Reference EP/L016796/1) is gratefully acknowledged.  ... 
arXiv:1902.04907v1 fatcat:7fwswxxuqfdovckubfzgvqbtwm

Software transparent dynamic binary translation for coarse-grain reconfigurable architectures

Matthew A. Watkins, Tony Nowatzki, Anthony Carno
2016 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
In this work we propose DORA, a Dynamic Optimizer for Reconfigurable Architectures, which achieves substantial (2X) power and performance improvements while having low hardware and insertion overhead and  ...  In addition to traditional optimizations, DORA leverages dynamic register information to perform optimizations not available to compilers and achieves performance similar to or better than CGRA-targeted  ...  ACKNOWLEDGMENTS We thank Karu Sankaralingam for his feedback as this work developed and for comments on draft versions of the paper.  ... 
doi:10.1109/hpca.2016.7446060 dblp:conf/hpca/WatkinsNC16 fatcat:ssmt2kzalba2xoozatcp6imlxq

Resource-efficient bio-inspired visual processing on the hexapod walking robot HECTOR

Hanno Gerd Meyer, Daniel Klimeck, Jan Paskarbeit, Ulrich Rückert, Martin Egelhaaf, Mario Porrmann, Axel Schneider, Olena Riabinina
2020 PLoS ONE  
Emulating the highly resource-efficient processing of visual motion information in the brain of flying insects, a bio-inspired controller for collision avoidance and navigation was implemented on a novel  ...  The system drastically outperforms CPU- and graphics card-based implementations in terms of speed and resource efficiency, making it suitable to be also placed on fast moving robots, such as flying drones  ...  Acknowledgments Many thanks to Timo Korthals for supporting the experiments in the Teleworkbench, Olivier Bertrand for hints and advices, Sina Gantenbrink for taking photographs and Jens Hagemeyer for  ... 
doi:10.1371/journal.pone.0230620 pmid:32236111 fatcat:wclrd2h2r5hdhkiwew2xck7maq

Multiprocessor System-on-Chip (MPSoC) Technology

W. Wolf, A.A. Jerraya, G. Martin
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture.  ...  The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. A wide range of MPSoC architectures have been developed over the past decade.  ...  Ackland and S. Dutta for the helpful discussions of their MPSoCs.  ... 
doi:10.1109/tcad.2008.923415 fatcat:p37pvh5iezfdjd4acepney4zmy

An Overview of Reconfigurable Hardware in Embedded Systems

Philip Garcia, Katherine Compton, Michael Schulte, Emily Blem, Wenyin Fu
2006 EURASIP Journal on Embedded Systems  
Reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems.  ...  This article presents an overview of reconfigurable computing in embedded systems, in terms of benefits it can provide, how it has already been used, design issues, and hurdles that have slowed its adoption  ...  Adding an FPGA power model [91] and using power-aware algorithms throughout the CAD flow can provide 26.5% power-delay product savings [90] . usually in a small area of the system.  ... 
doi:10.1186/1687-3963-2006-056320 fatcat:lybcy4xldvbvjhhzdci5ws37oy
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