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A proposed synthesis method for Application-Specific Instruction Set Processors

Péter Horváth, Gábor Hosszú, Ferenc Kovács
2015 Microelectronics Journal  
configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design.  ...  The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms  ...  Application-Specific Instruction Set Processors ASIPs represent special types of stored-program microprocessors, whose instruction set is optimized for a certain application or application domain.  ... 
doi:10.1016/j.mejo.2015.01.001 fatcat:6gu6fd2stnbpvcpfugaku3cnje

Custom Instruction Integration Method within Reconfigurable SoC and FPGA Devices

Yassine Aoudni, Guy Gogniat, Mohamed Abid, Jean-Luc Philippe
2006 2006 International Conference on Microelectronics  
was proposed as a case custom instruction opcode is added to the processor instruction study for experimentation. set.  ...  We propose a method to architecture.  ...  was proposed as a case custom instruction opcode is added to the processor instruction study for experimentation. set.  ... 
doi:10.1109/icm.2006.373284 fatcat:wjhslqgydnbm7cods2l3htghny

A method to derive application-specific embedded processing cores

Olivier Hébert, Ivan C. Kraljic, Yvon Savaria
2000 Proceedings of the eighth international workshop on Hardware/software codesign - CODES '00  
This paper proposes a method to derive applicationspecific embedded processors from soft processor cores.  ...  These soft cores are not tightly coupled with the target application, and this leads to processing cores sub-optimal for their specific applications.  ...  For example, if a processor has an instruction word of 8 bits, and a specific application only uses 30 different instructions, the instruction codes could be recoded to a word size of only 5 bits.  ... 
doi:10.1145/334012.334029 dblp:conf/codes/HebertKS00 fatcat:ud5bk6hxk5ftxevtg3bmufcuvy

Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs

Lech Jozwiak, Menno Lindwer
2011 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing  
This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors  ...  of MPSoCs for embedded applications.  ...  Most of the existing methods and tools of custom instruction-set construction are devoted to optimization of a single processor and are very simplistic.  ... 
doi:10.1109/pdp.2011.55 dblp:conf/pdp/JozwiakL11 fatcat:s7hkhc7gx5bhtnarwpquhwvc5m

Rapid generation of custom instructions using predefined dataflow structures

Siew-Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
2006 Microprocessors and microsystems  
In this paper, we propose an efficient methodology for rapid instruction set customization on RISPs (Reconfigurable Instruction Set Processors) using predefined sets of dataflow structures that are based  ...  Custom instruction generation is fast becoming popular as it provides an alternative means to realize application specific processors.  ...  Xtensa from Tensilica [3] , ARCtangent from ARC [4], etc.) offer the possibility of extending their instruction set for a specific application by introducing custom functional units within the processor  ... 
doi:10.1016/j.micpro.2006.02.012 fatcat:6awpowm6zvautlwvvhw2zuyhoy

Review on Scalable FFT Architecture for High Speed Communication Standard

2015 International Journal of Science and Research (IJSR)  
This paper presents a highly efficient hierarchical design of an application specific instruction set processor architecture exploration, software tools design, system verification and design implementation  ...  Simulation and synthesis results show that our FFT-ASIP achieves a higher energy-efficiency and flexibility and the area cost will be low.  ...  3]The paper by Xuan guan conferred a novel hierarchical design of an application-specific instruction set processor (ASIP) for high throughput FFT.  ... 
doi:10.21275/v4i11.nov151544 fatcat:ekfhjxfbu5gbtjlemgnqyvjz6u

Morphable Structures for Reconfigurable Instruction Set Processors [chapter]

Siew-Kei Lam, Deng Yun, Thambipillai Srikanthan
2005 Lecture Notes in Computer Science  
This paper presents a novel methodology for instruction set customization of RISPs (Reconfigurable Instruction Set Processors) using morphable structures.  ...  The utilization of a predefined set of morphable structures for instruction set customization dispenses the need for hardware synthesis in design exploration, and avoids run-time reconfiguration while  ...  Xtensa from Tensilica [3] , ARCtangent from ARC [4], etc.) offer the possibility of extending their instruction set for a specific application by introducing custom functional units within the processor  ... 
doi:10.1007/11572961_36 fatcat:5xk7n6kg3fctxe73mvjdqdn6sy

Application Specific Hardware Design Simulation for High Performance Embeddeed System

Ravi Khatwal, Manoj Kumar Jain
2014 International Journal of Computer Applications  
In this study the base instruction set with customized instructions, supported with specific hardware resources are analyzed.  ...  Xilinx provides SDK and XPS tools, XPS tools used for develop complete hardware platform and SDK provides software platform for application creation and verification.  ...  Hardware resources like processor; memories etc. easily implemented and analyzed custom instruction set behavior for specific application.  ... 
doi:10.5120/16834-6599 fatcat:4rbwuni6drdg3lhnidjf4e27fm

The Molen FemtoJava Engine

Julio B. Mattos, Stephan Wong, Luigi Carro
2006 IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)  
This allows for the existing FemtoJava to be augmented with reconfigurable hardware with only a single extension of the bytecodes and thereby but still allowing the implementation of arbitrary hardware  ...  Our experimental results on MP3 decoding, which is a common embedded application, can be improved by at least of 27% reduction of execution cycles with minimal additional hardware area (about 7%).  ...  Finally, we extended our Java processor with a reconfigurable hardware structure using the Molen approach that allows for the implementation of arbitrary function with a single instruction set extension  ... 
doi:10.1109/asap.2006.64 dblp:conf/asap/MattosWC06 fatcat:ev25cwkfpbe4fduhu4rw2nr3cu

ASAM: Automatic Architecture Synthesis and Application Mapping

Lech Jozwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri (+1 others)
2012 2012 15th Euromicro Conference on Digital System Design  
.  Abstract -This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable applicationspecific instruction-set  ...  processors (ASIPs).  ...  If after the initial selection and related data path synthesis the selected instruction set does not meet the design requirements, an instruction set extension can be proposed.  ... 
doi:10.1109/dsd.2012.28 dblp:conf/dsd/JozwiakLCMMMDGJPPTR12 fatcat:et5s2vcnhzbfrae2jufsqzq4gy

ADA: Applications Define ASIP

Manoj KumarJain
2014 International Journal of Computer Applications  
Interest in Application Specific Instruction set Processors or ASIPs has increased significantly.  ...  The Proposed technique does not focuses on design space exploration, it focuses on directly defining processors for given applications rather than searching for suitable configuration in a jungle of configurations  ...  RELATED WORK An Application Specific Instruction set Processor (ASIP) is a processor designed for one particular application or for a set of applications usually from a particular domain.  ... 
doi:10.5120/16663-6650 fatcat:dzdwjy7gajbz3nibkrpeqpjttq

A scalable application-specific processor synthesis methodology

F. Sun, S. Ravi, A. Raghunathan, N.K. Jha
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
Custom processors based on application-specific or domain-specific instruction sets are gaining popularity, and are often used to implement critical architectural blocks in complex system-on-chips.  ...  We present a scalable methodology for the synthesis of a custom processor from an embedded software program.  ...  Acknowledgments: This work was supported by the NJCST Center for Embedded System-on-a-chip Design.  ... 
doi:10.1109/iccad.2003.159702 fatcat:hzp77f2e5jf4dgorarwx7gycu4

Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)

Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura
2010 IPSJ Transactions on System LSI Design Methodology  
This paper introduces the concept and technology of Application-domain Specific Instruction-set Processor (ASIP).  ...  Next, processor hardware description synthesis technology, application program development tool set generation technology, and processor architecture optimization technology are outlined.  ...  .), for their effort to develop ASIP Meister. The author would like to thank Mr. Nobuyuki Hikichi from SRA, for his kind assistance and advice to the development of GNU tool set for ASIP Meister.  ... 
doi:10.2197/ipsjtsldm.3.161 fatcat:2utgua4qffep7ih5a2vbrl6lee

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize  ...  Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.  ...  The interface description of using hardware IP and instruction set for hardware IP generated by the processor core synthesis system are inputs for IFC Synthesizer.  ... 
doi:10.1145/1118299.1118440 fatcat:qx3emq7refgebnpalvsmxjwkqy

Micro embedded monitoring for security in application specific instruction-set processors

Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia
2005 Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems - CASES '05  
This paper presents a methodology for monitoring security in Application Specific Instruction-set Processors (ASIPs).  ...  Since ASIPs are designed exclusively for a particular application domain, the Instruction Set Architecture (ISA) of an ASIP is based on the application executed.  ...  In recent years, Application Specific Instruction-set Processors (ASIPs) [10] have gained popularity not only in the research community but also in the production of embedded systems.  ... 
doi:10.1145/1086297.1086337 dblp:conf/cases/RagelPK05 fatcat:aptyhg4o3jbyhg3tx52npfxs5u
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