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A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter
2014
IEEE Transactions on Electron Devices
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This paper explores the energy efficiency advantage of a 6-bit III-V heterojunction tunnel field-effect transistor (HTFET) based successive-approximation register (SAR) analogto-digital converter (ADC) ...
Compared with the Silicon FinFET (Si FinFET) ADC, the HTFET SAR ADC achieves approximately 3 times power consumption reduction and 6 times size reduction. ...
TFET ADVANTAGES AND MODELING METHODOLOGY FOR LOW-POWER ADC APPLICATION A. ...
doi:10.1109/ted.2014.2359663
fatcat:c7l4lyln4rh4lnefoin2p247ii
Low-Power Area-Efficient Decimation Filters in Sigma-Delta ADCs
2007
2007 IEEE Conference on Electron Devices and Solid-State Circuits
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In this implementation area-efficiency (as well as power-efficiency) is obtained by minimizing the capacitors size in the SAR DAC, which usually dominates the overall area budget in SAR ADCs 1 . ...
Pursuant to this aim, a design methodology is proposed to optimize both the power-and the area-efficiency of reconfigurable ADCs. ...
doi:10.1109/edssc.2007.4450255
fatcat:uciajdoalrdqnd2gy2ntdhwkoa
Low Power and High Speed SAR ADC-A Review
2021
International Journal of Engineering and Applied Sciences (IJEAS)
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It challenges analog designers to improve the Analog to Digital Converter (ADC) architectures. Thus leads their design to demand for a reduction in the power consumption. ...
Among the different Analog to digital convertors, Successive Approximation Register (SAR) Analog to digital convertor (ADC) is proven to provide results with lower power consumption and lesser area with ...
Capacitor-Based Bandpass Implementation Voltage Likelihood Energy of a SAR ADC ADC of Energy and Low Estimation Efficient low Employing a With Efficient SAR Power Based Switching power Passive Digitally ...
doi:10.31873/ijeas.8.7.03
fatcat:hadpf7fu6rhgzfmiv6soxb7cvy
Mixed-signal design space exploration of time-interleaved A/D converters for ultra-wide band applications
2008
Proceedings of the conference on Design, automation and test in Europe - DATE '08
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enabling the selection of two candidate implementations (a 6-bit 4.6-mW and a 7-bit 8.1-mW ADC targeting 1 GS/s) that effectively trade accuracy for energy efficiency and area. ...
Different speed/resolution scenarios are efficiently investigated and the impact of parallelism on system performance, yield and power consumption is assessed starting from the early design phases, finally ...
Conclusions We performed mixed-signal design space exploration of a TI SAR-ADC for UWB battery-powered consumer applications through a rigorous platform-based methodology. ...
doi:10.1145/1403375.1403710
fatcat:omac2y4fwrbvvbqjkhk4gxk4nm
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application
2020
Electronics
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The implemented SAR ADC consumes 14.8 µW power at 1 V power supply. ...
A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. ...
Conflicts of Interest: The authors declare no conflict of interest. ...
doi:10.3390/electronics9071100
fatcat:f5mpykb66vfhrl2bicsie32us4
Design techniques for nanometer wideband power-efficient CMOS ADCs
2011
2011 IEEE International Symposium on Radio-Frequency Integration Technology
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ADCs with high power efficiency in the state-of-the-art nanometer CMOS technology. ...
This paper will present the design techniques, including the architectural improvements, power reduction and linearity improvement techniques for successful implementation of various examples of high-speed ...
This paper will present the design considerations in nanometer CMOS technology which enable the implementation of wideband power efficient ADCs. ...
doi:10.1109/rfit.2011.6141760
fatcat:xudssfv5pvf75ir7b4bgtiqkpi
Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC
2021
Electronics
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The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. ...
efficiency. ...
When the SAR ADC needs to achieve high resolution, however, the comparator power and the size of a capacitive digital-to-analog converter (CDAC) increase exponentially, and the energy efficiency would ...
doi:10.3390/electronics10202545
fatcat:xkvinjouznamboceooydnfgjtm
A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology
2021
North atlantic university union: International Journal of Circuits, Systems and Signal Processing
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The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. ...
The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). ...
efficient SAR-ADC structure. ...
doi:10.46300/9106.2021.15.62
fatcat:6ppqbmc24jb4lcn4pcxt54jkxm
Feasibility of Successive Approximation Register ADC in Ultra Low Power Biomedical Applications
2017
International Journal of Engineering and Technology
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Hence, for biomedical implants which require ultra low power consumption and low complexity to reduce the size and cost of the devices, there is a need of energy-efficient ADCs that conform to these restraints ...
This paper presents a study on the feasibility of ultra low power Successive Approximation Register (SAR) ADC in these biomedical applications. ...
realm in terms of efficient design methodologies and circuit techniques. ...
doi:10.21817/ijet/2017/v9i3/170903s052
fatcat:rejlwfmab5gevohbchzuzxusyy
Analysis of Analog to Digital Converter for Biomedical Applications
2012
International journal of new practices in management and engineering
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The 10bit 1.8V rail-to-rail (SAR) ADC is realized using UMC 0.18µm CMOS process. Simulations are performed by spectre simulation. ...
For the low-power operation, monotonic switching scheme and operating voltage reduction have been implemented in the design. ...
Proposed Methodology The fundamental building blocks of the ADC comprises of a dynamic comparator, SAR controllable logic and series capacitor network. ...
doi:10.17762/ijnpme.v1i03.6
fatcat:ymi6twad3jg3zoj45h32kjloxi
A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-$\mu$m CMOS for Medical Implant Devices
2012
IEEE Journal of Solid-State Circuits
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Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. ...
This paper describes an ultra-low power SAR ADC for medical implant devices. ...
So far, most of the research on ADCs has been focused on moderate and particularly high-speed applications, while efficient design methodologies and circuit techniques for lowspeed and ultra-low-power ...
doi:10.1109/jssc.2012.2191209
fatcat:322xbu7donhvjl2z2bzkx4rxka
Introduction to the Special Issue on the 46th European Solid-State Circuits Conference (ESSCIRC)
2017
IEEE Journal of Solid-State Circuits
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His research domain is circuit level design of digital circuits. The current focus is on ultra-low power signal processing and memories in advanced CMOS technologies. ...
In July 2002 Wim Dehaene joined the staff of the ESAT-MICAS laboratory of the Katholieke Universiteit Leuven where he is now a full professor and head of the MICAS division. ...
ACKNOWLEDGMENT The Guest Editors would like to thank the authors for their firm commitment to write excellent manuscripts under a tight publication schedule. ...
doi:10.1109/jssc.2017.2711159
fatcat:hjuo7j3mxvfndgjesyt22gpkqy
An energy-efficient dual sampling SAR ADC with reduced capacitive DAC
2009
2009 IEEE International Symposium on Circuits and Systems
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This paper presents an energy-efficient SAR ADC which adopts reduced MSB cycling step with dual sampling of the analog signal. ...
Benefits from this technique, not only the total capacitance of DAC is reduced by half, but also the average switching energy is reduced by 68% compared with conventional SAR ADC. ...
Among many types of ADC, slope ADC, sigma-delta ADC and successive approximation register (SAR) ADC are good candidates for low power applications. ...
doi:10.1109/iscas.2009.5117920
dblp:conf/iscas/KimYYCY09
fatcat:ppy24gmyvbbvdnlg7oqr6iiwzu
A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC
2015
Journal of Integrated Circuits and Systems
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In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. ...
The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s. ...
This calculation shows that the sizing is not practical due to the excessive area and power consumption cost. However offset calibration is necessary to efficiently achieve good accuracy. ...
doi:10.29292/jics.v10i3.422
fatcat:bpxbi2vlwzgnvoyl6n7vvlhamq
Linearity analysis on a series-split capacitor array for high-speed SAR ADCs
2008
2008 51st Midwest Symposium on Circuits and Systems
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A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. ...
This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-tomedium-resolution SAR ADC. ...
This paper presents a novel structure of a split capacitor array to optimize the power efficiency and the speed of SAR ADCs. ...
doi:10.1109/mwscas.2008.4616951
fatcat:jn6ju7nhafa6bf6japgc7kmnxa
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