1,074 Hits in 13.6 sec

Process Variations and Process-Tolerant Design

Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
2007 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)  
To deal with increasing parameter variations, it is important to accurately model the impact of device parameter variations at circuit level and develop process-tolerant design techniques for both logic  ...  This article analyzes the impact of process parameter variations on logic circuits and memory and focuses on some major works in the area of process-tolerant design methodology at circuiffarchitecture  ...  Body bias can control leakage and performance of a die and thus has been investigated as a process adjustment tool.  ... 
doi:10.1109/vlsid.2007.131 dblp:conf/vlsid/BhuniaMR07 fatcat:haw2cidqhng7ngucgvwiftnsza

Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions

Swarup Bhunia, Kaushik Roy
2007 2007 IEEE International Test Conference  
Hence, there is a need to consider test and yield, while designing for low-power and robustness under variations.  ...  Numerous design techniques have been investigated for both logic and memory circuits to address the growing issues with power and variations.  ...  A practical application of body bias to adjust process variations requires accurate detection of process shift at different parts of a circuit and application of an optimal body bias voltage, which maximizes  ... 
doi:10.1109/test.2007.4437659 dblp:conf/itc/BhuniaR07 fatcat:bdsfonjkkrhnxeigu3gog4y6de

A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits

Baozhen Yu, Michael L. Bushnell
2006 Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED '06  
First, the switching window for each gate, during which a gate makes its transitions, is identified by static timing analysis.  ...  In this thesis, we present a novel active leakage power reduction technique using dynamic power cutoff, called the dynamic power cutoff technique (DPCT).  ...  Another way for dynamic threshold design is to control the body bias voltage dynamically through a bias-control circuit depending on the workload of the system.  ... 
doi:10.1145/1165573.1165627 dblp:conf/islped/YuB06 fatcat:gfwymnkavna3pes4oiescxdamm

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

B.H. Calhoun, Yu Cao, Xin Li, Ken Mai, L.T. Pileggi, R.A. Rutenbar, K.L. Shepard
2008 Proceedings of the IEEE  
How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution.  ...  usually chosen as minimum for most digital circuits, is emerging as an optimization parameter as well, as V T and output conductance (drain-inducted barrier lowering) become strongly dependent on L [4  ...  Program, in particular, their support of C2S2. They are also grateful to their many faculty and student colleagues in C2S2 for their ideas and inputs on this paper.  ... 
doi:10.1109/jproc.2007.911072 fatcat:dxmkxqiazffjzfv24okubw4zeu

VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width

K Kunaparaju, S Narasimhan, S Bhunia
2011 2011 24th Internatioal Conference on VLSI Design  
In case of body biasing we use Forward Body Bias(FBB) since it is the most effective way to reduce both active and leakage power and improve the performance of the circuit.  ...  The threshold voltage of each die is controlled not only by process but also by the application of the appropriate amount of Forward Body Bias(FBB) or Reverser Body Bias(RBB).  ...  An FIR filter is usually implemented by using building blocks like delay elements, multipliers, and adders to create the filter's output.  ... 
doi:10.1109/vlsid.2011.58 dblp:conf/vlsid/KunaparajuNB11 fatcat:lyjvho7l7zct7fd36gfucaztzy

Practical Strategies for Power-Efficient Computing Technologies

L. Chang, D.J. Frank, R.K. Montoye, S.J. Koester, B.L. Ji, P.W. Coteus, R.H. Dennard, W. Haensch
2010 Proceedings of the IEEE  
Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system.  ...  It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized  ...  Acknowledgment The authors would like to thank all of their colleagues at IBM for invaluable discussions, criticism, and guidance. In particular, the authors would like to acknowledge A.  ... 
doi:10.1109/jproc.2009.2035451 fatcat:hp3zqxde7vakvd7xzvu7l6wcga

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Jeren Samandari-Rad, Richard Hughey
2016 IEEE Access  
Power and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs.  ...  Using exVAR-TX for architectural optimization [exhaustively computing and comparing the range of feasible architectures subject to interdie (die-to-die/D2D) and intradie (within-die/WID) process and operation  ...  Stringent control of the MOSFET characteristics, either at process time or at run time using techniques such as body biasing, is essential in the low voltage operation mode [3] .  ... 
doi:10.1109/access.2016.2521385 fatcat:vowwzjai7jhg3iezcclnpdph3e

Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS

Dennis Sylvester, Ashish Srivastava
2007 Proceedings of the IEEE  
However, using the same body bias for the entire design results in a highly constrained problem and degrades power improvements.  ...  The results showed that the technique can improve the yield of a design by as much as 40% over a deterministically optimized design. VI.  ... 
doi:10.1109/jproc.2006.889370 fatcat:nwrtqso5rjdn3n4hpkytn3bppi

Statistical Approach for Yield Optimization for Minimum Energy Operation in Subthreshold Circuits Considering Variability Issues

M.W.K. Nomani, M. Anis, G. Koley
2010 IEEE transactions on semiconductor manufacturing  
design constraints, variations in the design variables due to manufacturing uncertainty, device sizing, activity factor of the circuit, and power reduction techniques.  ...  By using this methodology, yield is found to be strongly dependent on the design metrics, circuit switching activity, transistor sizing, and the given constraints.  ...  Ponnambalam of the University of Waterloo for providing the preliminary MATLAB codes of the optimization problem.  ... 
doi:10.1109/tsm.2009.2039184 fatcat:4vpmzcohdff2rngk7atn4fja7a

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

Georgios Karakonstantis, Abhijit Chatterjee, Kaushik Roy
2011 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased  ...  This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting  ...  Sen, and S. Devarakond for their contributions to the work discussed in Sections III and IV.  ... 
doi:10.1109/jetcas.2011.2135590 fatcat:3tnl6lww3jesfmv5ptqgpv45le

Benefits of decomposing wide CMOS transistors into minimum-size gates

Hans Kristian Otnes Berge, Snorre Aunet
2009 2009 NORCHIP  
For digital circuit design in the subthreshold domain the analysis of Paper VI shows a possible path for how combined effects of RDF variability and complexity can be estimated very early in the design  ...  body bias coefficient (written as γ b s and λ b s in the previous section), LPE0 and LPEB are respectively the zero body bias, and body bias dependent, lateral non-uniform doping parameters.  ... 
doi:10.1109/norchp.2009.5397795 fatcat:rr6gli6uxngtxfzm5zk2t5azfq

Design, Automation, and Test for Low-Power and Reliable Flexible Electronics

Tsung-Ching Huang, Jiun-Lang Huang, Kwang-Ting Cheng
2015 Foundations and Trends® in Electronic Design Automation  
We will then give an overview of digital and analog circuit design from basic logic gates to a microprocessor, as well as design automation tools and methods, for designing flexible electronics.  ...  , large process variation, and lack of trustworthy device modeling also make designing larger-scale and robust TFT circuits a significant challenge.  ...  The technique starts from fresh yield optimization; the resulting design is optimized again for lifetime yield (using the degraded device parameters).  ... 
doi:10.1561/1000000039 fatcat:n6vf2kzcprbt7aojy6u74inkui

An adaptive FPGA architecture with process variation compensation and reduced leakage

G. Nabaa, N. Azizi, F.N. Najm
2006 Proceedings - Design Automation Conference  
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield.  ...  This procedure mitigates the effect of the variations and provides a better yield. We further diminish leakage by slowing down areas of the FPGA that have a positive slack.  ...  Acknowledgments The authors would like to acknowledge the technical guidance and support of Nizar Abdallah and Amal Zerrouki at Actel Corporation  ... 
doi:10.1109/dac.2006.229308 fatcat:sbaexz6mz5fr3by65wakngm5vq

Overcoming Variations in Nanometer-Scale Technologies

Sachin S. Sapatnekar
2011 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
Such problems have led to a revolution in the way that chips are designed in the presence of such uncertainties, both in terms of performance analysis and optimization.  ...  parameters and as circuit aging effects.  ...  Optimization Process variations can significantly degrade the yield of a circuit, and optimization techniques can be used to improve the timing yield.  ... 
doi:10.1109/jetcas.2011.2138250 fatcat:fo5udiv7mzc2po2uwspuj2ebzy

Optimal design of a dual-oxide nano-CMOS universal level converter for multi-V dd SoCs

Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah
2012 Analog Integrated Circuits and Signal Processing  
The paper further proposes a novel design methodology accompanied by an optimization algorithm for the parasitic-aware power-delay optimization of the ULC circuit.  ...  The entire design has been implemented in 90 nm CMOS up to layout, including DRC/LVS and parasitic (RC) re-simulation, and was subjected to process variation of 10 process parameters.  ...  Acknowledgements This research is supported in part by NSF awards CNS-0854182 and DUE-094262. The authors would like to acknowledge Dr. Dhruva Ghai, graduate of the University of North Texas.  ... 
doi:10.1007/s10470-012-9887-7 fatcat:qbgnha7asbb5fiwoap437oojo4
« Previous Showing results 1 — 15 out of 1,074 results