Filters








35 Hits in 6.8 sec

Hardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband Applications

Mahmud Benhamid, Masuri Bin Othman
2009 Journal of Mathematics and Statistics  
Approach: Based on the algorithm and architecture analysis, a novel Genetic Algorithm (GA) based Canonical Signed Digit (CSD) Multiplier less 128-point FFT processor and its inverse (IFFT) for MB-OFDM  ...  The proposed pipelined architecture was based on the modified Radix-2 2 algorithm that had same number of multipliers as that of the conventional Radix-2 2 .  ...  In 1998, He and Torkeson [6] suggested radix-2 2 and radix-2 3 FFT algorithms.  ... 
doi:10.3844/jmssp.2009.241.250 fatcat:nh67rdxkofbpbg7j4np6jtdgfy

A Novel Architecture for Radix-4 Pipelined FFT Processor using Vedic Mathematics Algorithm

K Naresh, Dr. G. Sateesh Kumar
2014 IOSR Journal of Electronics and Communication Engineering  
In this study, an efficient addressing scheme for radix-4 64 point FFT processor is presented.  ...  The FFT processor is a critical block in all multi-carrier systems used primarily in the mobile environment.  ...  A Novel Architecture for Radix-4 Pipelined FFT Processor using Vedic Mathematics Algorithm www.iosrjournals.org  ... 
doi:10.9790/2834-09622331 fatcat:zg4yrrwlmzgujaeol6v77pum5y

Design and Implementation of Novel Multiplier using Barrel Shifters

Neeta Pandey, Saurabh Gupta
2015 International Journal of Image Graphics and Signal Processing  
The paper presents a design scheme to provide a faster implementation of multiplication of two signed or unsigned numbers.  ...  It provides a uniform architecture which makes upgrading to a bigger multiplier much easier than other schemes.  ...  Parallel-prefix adder tree structures such as Kogge-Stone [9] , Sklansky [10] , Brent-Kung [11] , Han-Carlson [12] , and Kogge-Stone using Ling adders [13] etc. have one or other advantage over other  ... 
doi:10.5815/ijigsp.2015.08.03 fatcat:nynxlhpuf5agvguu3pl4n4syrm

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

Alfonso Troya, Koushik Maharatna, Milo¿ Krstic, Eckhard Grass, Ulrich Jagdhold, Rolf Kraemer
2008 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arctangent computation unit, numerically controlled oscillator  ...  These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25-m 5-metal layer BiCMOS technology from Institute for High Performance  ...  Gunzelmann for their unconditional support in publishing this paper. They also would like to thank Prof. A.  ... 
doi:10.1109/tcsi.2007.913732 fatcat:zri3wo6sqfd7rmiwwl4cr7iyie

FPGA Implementation of high speed-low energy RNS based Reconfigurable-FIR Filter for Cognitive Radio Applications

C. Srinivasa Murthy, K. Sridevi
2021 WSEAS transactions on systems and control  
In this paper, we present a high-performance RNS based FIR filter design for filtration in SDR applications.  ...  A distinctive feature of the proposed FIR filter implementation with core optimized RNS is to minimize hardware complexity overhead with the improved operating speed.  ...  Moreover, this path delay is further optimized using modified parallel prefix adder topology-based accumulation within the RNS system in the proposed method in existing designs and the detailed information's  ... 
doi:10.37394/23203.2021.16.24 fatcat:rjxwaqhut5b57mjvex475wl34e

STBC-OFDM Downlink Baseband Receiver for Mobile WMAN

Hsiao-Yun Chen, Jyun-Nan Lin, Hsiang-Sheng Hu, Shyh-Jye Jou
2013 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper proposes a space time block code-orthogonal frequency division multiplexing downlink baseband receiver for mobile wireless metropolitan area network.  ...  It requires a core area of mm and dissipates 68.48 mW at 78.4 MHz with 1 V power supply.  ...  Fig. 11 . 11 Radix-8 1024-point parallel memory-based FFT architecture. Fig. 12 . 12 Radix-8 processing element. Fig. 14 . 14 Flow chart of the proposed receiver.  ... 
doi:10.1109/tvlsi.2011.2181965 fatcat:bvh5n2idondd5era5d4hculibi

Implementation Approaches Trade-Offs for WiMax OFDM Functions on Reconfigurable Platforms

Ahmad Sghaier, Shawki Areibi, Robert Dony
2010 ACM Transactions on Reconfigurable Technology and Systems  
The Tensilica Xtensa processor approach presented remarkable figures, in terms of power, area and design time.  ...  The custom RTL approach showed the ability of a medium size FPGA to accommodate the design with only 50% occupation rate. The AccelDSP approach showed an area overhead of 10%.  ...  The main contribution is attributed to the study of the effect of using only one Radix-4 FFT processor or Radix-2 pipelined streaming FFT processor, instead of using as many FFT processors as the number  ... 
doi:10.1145/1839480.1839482 fatcat:bgnljutmljdcpihgcso5p7cpae

High Performance Quantum Modular Multipliers [article]

Rich Rines, Isaac Chuang
2018 arXiv   pre-print
We present a novel set of reversible modular multipliers applicable to quantum computing, derived from three classical techniques: 1) traditional integer division, 2) Montgomery residue arithmetic, and  ...  Each multiplier computes an exact result for all binary input values, while maintaining the asymptotic resource complexity of a single (non-modular) integer multiplier.  ...  For a multi-bit adder, a parallel network can be used to compute the prefix bits. For classical, non-reversible, adders many networks have been proposed and used to create adders.  ... 
arXiv:1801.01081v1 fatcat:euefn5f7yjf4dhw7mgv5qypccu

Table of contents

2004 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat No 04CH37512) ISCAS-04  
AND MULTIPLIERS VLSI-L12.1: DYNAMIC PASS-TRANSISTOR DOT OPERATORS FOR EFFICIENT ..............................................II -461 PARALLEL-PREFIX ADDERS Henrik Eriksson, Per Larsson-Edefors, Chalmers  ...  Nguyen, Soontorn Oraintara, University of Texas, Arlington, United States DSP-L9.3: EFFICIENT OUTPUT-PRUNING OF THE 2-D FFT ALGORITHM.........................................................  ... 
doi:10.1109/iscas.2004.1328114 fatcat:xmvsmkhxgbb55ftuygqomthikm

Signal definition and resource management techniques for upcoming communication and broadcasting systems

Charbel Abdel Nour
2020 Zenodo  
This work was the subject of 2 PhDs (1 awarded URSI Radioscience PhD prize in 2019) and 2 post-docs.  ...  for severe channel conditions and the support of high throughput.  ...  parallelism [77] or high-order radix decoding [78] .  ... 
doi:10.5281/zenodo.4968707 fatcat:d2zvqd5l5vhq7j6li5kwyc65je

Signal definition and resource management techniques for upcoming communication and broadcasting systems

Charbel Abdel Nour
2020 Zenodo  
This work was the subject of 2 PhDs (1 awarded URSI Radioscience PhD prize in 2019) and 2 post-docs.  ...  for severe channel conditions and the support of high throughput.  ...  parallelism [77] or high-order radix decoding [78] .  ... 
doi:10.5281/zenodo.5020532 fatcat:nlqm7ld62nhpxiygmjt5sy5m54

Design of a Low Power and Area Efficient Architecture for the Detection of Audio Biological Signals

Sangavi. J
2018 International Journal for Research in Applied Science and Engineering Technology  
In digital audio recording the audio signals are picked by a microphone or other transducer and converted into a stream of discrete numbers, representing the changes over time in air pressure for audio  ...  Thus the aim of the proposed work is to design a low power and area efficient mathematical architecture for the calculation of energy parameter, coastline parameter, quasi-average and Mel Cepstrum based  ...  Thus for more efficient computation or parallel implementation of the 2-D DCT, the algorithms that work directly on the 2-D data set has to be introduced.  ... 
doi:10.22214/ijraset.2018.4694 fatcat:5rwnt2h3czcmbldgarntvwdnve

Towards Designing Asynchronous Microprocessors: From Specification to Tape-out

Zaheer Tabassam, Syed Rameez Naqvi, Tallha Akram, Musaed Alhussein, Khursheed Aurangzeb, Sajjad Ali Haider
2019 IEEE Access  
mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors.  ...  Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing  ...  The algorithms bilinear demosaicing [122] , 8K-point radix-2 1-D FFT [123] and 2-D DCT [124] are the benchmarks for the evaluation of the design.  ... 
doi:10.1109/access.2019.2903126 fatcat:rwtsay62xbenhn5cgwzszhf4lm

Computational Power Evaluation for Energy-Constrained Wireless Communications Systems

M. Tariq, A. Al-Dweik, B. Mohammad, H. Saleh, T. Stouraitis
2020 IEEE Open Journal of the Communications Society  
Therefore, this paper presents a novel approach, based on practical system measurements using field programmable gate array (FPGA) and application-specific integrated circuit (ASIC), to evaluate the power  ...  This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 308 VOLUME 1, 2020  ...  Alouini for the valuable feedback and comments and discussions.  ... 
doi:10.1109/ojcoms.2020.2982355 fatcat:zqyh36rofneldbhomocsdsd4ey

DESIGN OF NOVEL MIMO-OFDM USING RANDOM INTERLEAVER FOR 4G WIRELESS COMMUNICATION

G Gangaram, Muthu
2014 International Journal of Recent Development in Engineering and Technology Website: www.ijrdet.com   unpublished
The radix-2 with bit reversal FFT architecture is proposed to efficiently deal with data sequences.  ...  In this paper present a pipelined Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n  ...  This indicates that a radix-4 FFT can be four times faster than a radix-2 FFT. Fig 6 shows a diagram for an 64-point radix-2 DIT-FFT (decimation in time-FFT).  ... 
fatcat:akby2hzybnbqrjjbinnrouswya
« Previous Showing results 1 — 15 out of 35 results