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A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components [article]

Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas, Vianney Lapôtre, Guy Gogniat
2018 arXiv   pre-print
This work proposes a novel way to instrument an application with minor modifications, at the source code level, taking advantage of underlying hardware debug components such as CS (CoreSight) components  ...  Most of hardware-assisted solutions for software security, program monitoring, and event-checking approaches require instrumentation of the target software, an operation which can be performed using an  ...  This paper puts forward a novel approach for static instrumentation that can be used on ARM SoCs with CS (CoreSight) debug components [8] .  ... 
arXiv:1812.01667v1 fatcat:a2kvjywl5raqzkbgigtwlgeore

A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components

Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat, Arnab Kumar Biswas
2018 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)  
A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components.  ...  This work proposes a novel way to instrument an application, at the source code level, taking advantage of underlying hardware debug components such as CS (CoreSight) components available on Xilinx Zynq  ...  This work puts forward a novel approach for static instrumentation that can be used on ARM SoCs with CS (CoreSight) debug components.  ... 
doi:10.1109/asianhost.2018.8607177 dblp:conf/asianhost/WahabCAHLGB18 fatcat:6bmpvnntpzb6ze5wioy7bpfqgi

NUDA: A Non-Uniform Debugging Architecture and Nonintrusive Race Detection for Many-Core Systems

Chi-Neng Wen, Shu-Hsuan Chou, Chien-Chih Chen, Tien-Fu Chen
2012 IEEE transactions on computers  
Our approach makes hardware-assisted debugging both feasible and scalable for many-core processing scenarios.  ...  The first contribution of this paper is to propose a novel non-uniform debugging architecture (NUDA) based on a ring interconnection schema.  ...  There are several hardware approaches for debugging.  ... 
doi:10.1109/tc.2010.254 fatcat:6bcrurc6p5aenojnwikfsqhvcy

Hardware supported Software and Control Flow Integrity

Ruan de Clercq
2017 Zenodo  
This includes a detailed description and comparison of each architecture's policies, security, hardware cost, performance, and suitability for widespread deployment.  ...  All the architectures developed in this thesis are evaluated on FPGA, which allows us to accurately determine the hardware cost and the performance overhead of running the software on the architecture.  ...  The architecture works as a standalone IP core inside a System-on-Chip (SoC), which is a novel approach to enforce a hardware-based security policy.  ... 
doi:10.5281/zenodo.2643373 fatcat:3elmla7my5fa5jyeti73b7pnkm

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

Jaume Joven, Akash Bagdia, Federico Angiolini, Per Strid, David Castells-Rufas, Eduard Fernandez-Alonso, Jordi Carrabina, Giovanni De Micheli
2013 IEEE Transactions on Industrial Informatics  
which has been tailored for a distributed-shared memory ARM clustered NoC-based MPSoC platform.  ...  In this paper, we present a hardware-software QoS-driven reconfigurable parallel computing framework, i.e., the NoC services, the runtime QoS middleware API and our ocMPI library and its tracing support  ...  This implementation leads to a lightweight message-passing library that only uses of memory footprint (using ), which is suitable for distributed-memory embedded and clustered SoCs.  ... 
doi:10.1109/tii.2012.2222035 fatcat:26afuvlu7je5pdx2kmreq4mgxe

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

V.A. Chouliaras, D. Stevens, V.M. Dwyer
2016 Microprocessors and microsystems  
Abstract We discuss VThreads, a novel VLIW CMP with hardware-assisted shared-memory Thread support.  ...  VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads. Microprocessors and Microsystems, 47 pt.B, pp.466-485.  ...  Return when all HCs are in DEBUG mode vtApiIssueDbgCmdAndWaitFor Completion Wait for execution of Debug command on addressed <S.C.HC> (b) VTAPI Set 2 Instrumentation vtApiSetUpInstrumentation Attach  ... 
doi:10.1016/j.micpro.2016.07.010 fatcat:quypmfdiybggpbjzakwdcndlg4

User-Space Emulation Framework for Domain-Specific SoC Design [article]

Joshua Mack, Nirmal Kumbhare, Anish NK, Umit Y. Ogras, Ali Akoglu
2020 arXiv   pre-print
In this work, we propose a portable, Linux-based emulation framework to provide an ecosystem for hardware-software co-design of Domain-specific SoCs (DSSoCs) and enable their rapid evaluation during the  ...  of CPU cores and FFT accelerators using a Zynq UltraScale+TM MPSoC.  ...  Considering a three layered approach to SoC design with hardware, resource management and application layers, both, discrete-event [13] , [14] and cycle-accurate [15] - [17] based simulation approaches  ... 
arXiv:2004.01636v2 fatcat:juiy5ehgmvbfbjs2qodhg3yo3i

New Frontiers in IoT: Networking, Systems, Reliability, and Security Challenges [article]

Saurabh Bagchi, Tarek F. Abdelzaher, Ramesh Govindan, Prashant Shenoy, Akanksha Atrey, Pradipta Ghosh, Ran Xu
2020 arXiv   pre-print
We conclude by providing a vision for a desirable end state for IoT systems.  ...  The unique challenges arise from the unique characteristics of IoT systems such as the diversity of application domains where they are used and the increasingly demanding protocols they are being called  ...  For example, an IO register on one system may unlock a lock while on a different system, it may control an LED used for debugging.  ... 
arXiv:2005.07338v1 fatcat:a6hb5dpk7fgwreua5x2n7vlw7y

Supporting Transparent Snapshot for Bare-metal Malware Analysis on Mobile Devices

Le Guan, Shijie Jia, Bo Chen, Fengwei Zhang, Bo Luo, Jingqiang Lin, Peng Liu, Xinyu Xing, Luning Xia
2017 Proceedings of the 33rd Annual Computer Security Applications Conference on - ACSAC 2017  
In addition, all of the existing works require some in-guest components to assist the restoration. Therefore, a kernel-level malware is still able to detect the presence of the in-guest components.  ...  Memory snapshot is enabled by an isolated operating system (BoltOS) in the ARM Trust-Zone secure world, and disk snapshot is accomplished by a piece of customized firmware (BoltFTL) for flash-based block  ...  ACKNOWLEDGMENTS The authors would also like to thank the anonymous referees for their valuable comments and helpful suggestions. The work is sup-  ... 
doi:10.1145/3134600.3134647 dblp:conf/acsac/GuanJCZLLLXX17 fatcat:6sgozgloofbwvkqzawixtlkxma

CFI CaRE: Hardware-Supported Call and Return Enforcement for Commercial Microcontrollers [chapter]

Thomas Nyman, Jan-Erik Ekberg, Lucas Davi, N. Asokan
2017 Lecture Notes in Computer Science  
CaRE uses a novel way of protecting the CFI metadata by leveraging TrustZone-M security extensions introduced in the ARMv8-M architecture.  ...  Its binary instrumentation approach preserves the memory layout of the target MCU software, allowing pre-built bare-metal binary code to be protected by CaRE.  ...  Research Institute for Secure Computing (ICRI-SC).  ... 
doi:10.1007/978-3-319-66332-6_12 fatcat:46pijrpwjbhhzo5vovgzxivd3e

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Javad Zarrin, Rui L. Aguiar, João Paulo Barraca
2017 Simulation modelling practice and theory  
Novel systems must be designed with great care and tools, such as manycore architecture simulators, must be adapted accordingly.  ...  The aim of this work is to highlight how current approaches can best deal with the identified problems, smoothing the challenges of research in future peta-scale systems.  ...  SoC architecture integrates all components of a (electronic/computing) system (including complex hardware/software) into a single integrated concept.  ... 
doi:10.1016/j.simpat.2016.12.014 fatcat:j2acoyv235awfjkz6w7krvzh44

OAT: Attesting Operation Integrity of Embedded Devices [article]

Zhichuang Sun, Bo Feng, Long Lu, Somesh Jha
2019 arXiv   pre-print
OAT also features lightweight integrity checking for critical data (74% fewer instrumentation needed than previous work).  ...  We then design and build a system, OAT, that enables remote OEI attestation for ARM-based bare-metal embedded devices.  ...  The only hardware requirement OAT has is the TrustZone extension, which is available on many commercial embedded ARM SoCs. We used OP-TEE [45] as our TEE OS (the OS for the Secure World).  ... 
arXiv:1802.03462v3 fatcat:u3ogiw5tpreebnt5skmzshjo2i

PTAuth: Temporal Memory Safety via Robust Points-to Authentication [article]

Reza Mirzazade Farkhani, Mansour Ahmadi, Long Lu
2020 arXiv   pre-print
PTAuth contains a customized compiler for code analysis and instrumentation and a runtime library for performing the points-to authentication as a protected program runs.  ...  To address these limitations, we present robust points-to authentication, a novel runtime scheme for detecting all kinds of temporal memory corruptions.  ...  Acknowledgment The authors would like to thank the anonymous reviewers for their help with the revision of this paper.  ... 
arXiv:2002.07936v3 fatcat:plkz7dgqe5grxjvhmubrx6ka4m

KVM/ARM

Christoffer Dall, Jason Nieh
2014 Proceedings of the 19th international conference on Architectural support for programming languages and operating systems - ASPLOS '14  
We provide the first measurements on real hardware of a complete hypervisor using ARM hardware virtualization support.  ...  As ARM CPUs become increasingly common in mobile devices and servers, there is a growing demand for providing the benefits of virtualization for ARM-based devices.  ...  An earlier prototype for KVM on ARM [12, 15] used an automated lightweight paravirtualization approach to automatically patch kernel source code to run as a guest kernel, but had poor performance.  ... 
doi:10.1145/2541940.2541946 dblp:conf/asplos/DallN14 fatcat:wxyhypd6xfgi5ko3rx7jjfsdku

The hArtes Tool Chain [chapter]

Koen Bertels, Ariano Lattanzi, Emanuele Ciavattini, Ferruccio Bettarelli, Maria Teresa Chiaradia, Raffaele Nutricato, Alberto Morea, Anna Antola, Fabrizio Ferrandi, Marco Lattuada, Christian Pilato, Donatella Sciuto (+10 others)
2012 Hardware/Software Co-design for Heterogeneous Multi-core Platforms  
Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain, chapter The hArtes Tool Chain, pages 9-109.  ...  Debug support We used Gnu DeBugger (GDB) targeted for ARM Linux, plus an additional hArtes patch to support multiple PE.  ...  In the following chapters will be described techniques to debug an hArtes application for GPP+DSP. For the GPP and DSP we use the GNU GDB targeted for ARM and customized for hArtes.  ... 
doi:10.1007/978-94-007-1406-9_2 fatcat:izopdxmxxnegnotxjvvcqmle3i
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