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A novel high throughput reconfigurable FPGA architecture

Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska
<span title="">2000</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/onq43wd7gna3zbic6lchssp6ke" style="color: black;">Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA &#39;00</a> </i> &nbsp;
In this paper, we propose a novel high throughput FPGA architecture which tries to combine the high-performance of Application Specific Integrated Circuits (ASICs) and the flexibility afforded by the reconfigurability  ...  However, most commercial FPGAs, due to their general purpose architectural nature, cannot handle designs which require very high throughput.  ...  Conclusions We have proposed a novel FPGA architecture that combines the high performance of ASICs and the flexibility afforded by reconfigurable logic.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/329166.329174">doi:10.1145/329166.329174</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/fpga/SinghMMM00.html">dblp:conf/fpga/SinghMMM00</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/2fukt3dcvndrffoasrevnp3ziq">fatcat:2fukt3dcvndrffoasrevnp3ziq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808221916/http://www.cecs.uci.edu/~papers/compendium94-03/papers/2000/fpga00/pdffiles/1_3.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f9/4c/f94c3eb7faee6caf9e8cc037056e8ad6e257ccfb.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/329166.329174"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

An FPGA-based Accelerator for Deep Neural Network with Novel Reconfigurable architecture

Han Jia, Daming Ren, Xuecheng Zou
<span title="">2021</span> <i title="Institute of Electronics, Information and Communications Engineers (IEICE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fvf4s3u4inbjpnfv6imirwcvam" style="color: black;">IEICE Electronics Express</a> </i> &nbsp;
This paper presents a novel reconfigurable architecture as DNN accelerate solution, which consists of circuit blocks all can be reconfigured to adapt to different networks, and maintain high throughput  ...  Compared to other state-of-theart solutions based on FPGA, our architecture achieves high performance, and presents good flexibility in the meantime.  ...  In this paper, a novel reconfigurable architecture is proposed to deal with diverse DNN models while maintaining high performance.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.18.20210012">doi:10.1587/elex.18.20210012</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/fcmswhhikzaq7dmz22jhy2kwvm">fatcat:fcmswhhikzaq7dmz22jhy2kwvm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20210717163313/https://www.jstage.jst.go.jp/article/elex/18/4/18_18.20210012/_pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/b9/79/b979d959d44cba89a3b81297bea5504d6facff1d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.18.20210012"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Cover and Frontmatter

<span title="">2008</span> <i title="IEEE"> 2008 International Conference on Application-Specific Systems, Architectures and Processors </i> &nbsp;
Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards ...................................................................... 209 • Architecture and VLSI Realization of a High-Speed  ...  TABLE O O Session 2: System-level Interconnect and Mapping in SoCs ........................... 61 • A New High-Performance Scalable Dynamic Interconnection for FPGA-based Reconfigurable Systems .......  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/asap.2008.4580202">doi:10.1109/asap.2008.4580202</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ylw2sim6gnb2hbh3qjnkbcepwu">fatcat:ylw2sim6gnb2hbh3qjnkbcepwu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170830164407/https://www.computer.org/csdl/proceedings/asap/2008/1897/00/CoverandFrontMatter.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/04/d5/04d5c0d621052ccbf095334f96a5fdee98cf2a40.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/asap.2008.4580202"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

A RECONFIGURABLE ARCHITECTURE OF TURBO DECODER FOR MIMO-HIGH SPEED DOWNLINK PACKET ACCESS

Yasodha
<span title="2014-06-01">2014</span> <i title="Science Publications"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/myyqjkgwizb57p75zpb2nhqvpe" style="color: black;">American Journal of Applied Sciences</a> </i> &nbsp;
To attain effective performance close to shannon limit in a multi channel system, flexible reconfigurable architecture is realized with 28 nm cyclone V GX 5CGXFC5C6 FPGA.  ...  This study comprises the design and performance evolution of the proposed reconfigurable architecture for channel coding scheme in MIMO-High Speed Downlink Packet Access (MIMO-HSDPA).  ...  The novel hybrid last level cache architecture (Fig. 4) adopts to different modulation schemes such as QPSK, 16-QAM and 64-QAM.To improve the throughput of the system, a reconfigurable system is developed  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3844/ajassp.2014.883.887">doi:10.3844/ajassp.2014.883.887</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gwjxouvcq5ahjoiqmawmbsgn74">fatcat:gwjxouvcq5ahjoiqmawmbsgn74</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809074937/http://thescipub.com/PDF/ajassp.2014.883.887.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/73/35/7335a744d796136f76f1c09a2205f3f0658ed932.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3844/ajassp.2014.883.887"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

fpgaConvNet: A Toolflow for Mapping Diverse Convolutional Neural Networks on Embedded FPGAs [article]

Stylianos I. Venieris, Christos-Savvas Bouganis
<span title="2017-11-23">2017</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
In recent years, Convolutional Neural Networks (ConvNets) have become an enabling technology for a wide range of novel embedded Artificial Intelligence systems.  ...  Across the range of applications, the performance needs vary significantly, from high-throughput video surveillance to the very low-latency requirements of autonomous cars.  ...  Graph partitioning with reconfiguration is tailored to high-throughput applications and achieves high throughput by partitioning a ConvNet along its depth and constructing one SDF subgraph per partition  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1711.08740v1">arXiv:1711.08740v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/byjd5x72p5ekja5jjekms6knle">fatcat:byjd5x72p5ekja5jjekms6knle</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200830151636/https://arxiv.org/pdf/1711.08740v1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/92/dc/92dca3910333489c16d348958f6ecf717ba9ae60.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1711.08740v1" title="arxiv.org access"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> arxiv.org </button> </a>

Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture

Zong Wang, Tughural Arslan, Ahmet Erdogan
<span title="">2008</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/4s2ejwsygze4vfu5lsndw5m4ny" style="color: black;">4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)</a> </i> &nbsp;
The implementations target a novel Reconfigurable Instruction Cell Array (RICA) based architecture which has recently been developed [8], with the aim of achieving low power, high performance and programming  ...  As our simulation result shows, RC4 stream cipher throughput achieves as high as 60 Mbps with 128 bits key size and 1024 bits data buffer packet.  ...  Our architecture can not beat the high end FPGA solutions on AES algorithm in terms of throughput but in power and area.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/delta.2008.100">doi:10.1109/delta.2008.100</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/delta/WangAE08.html">dblp:conf/delta/WangAE08</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ykxr77ph4zevbltzm4m4bmggti">fatcat:ykxr77ph4zevbltzm4m4bmggti</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20120713221920/http://www.see.ed.ac.uk/~SLIg/papers/wang_DELTA08.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f9/c5/f9c5f3e45516ac22dfa0b773ff8f50973cb6d14c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/delta.2008.100"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)

Massimo Conti, Elmar Melcher, Jürgen Becker, Alisson Brito, Oliver Sander
<span title="">2013</span> <i title="Hindawi Limited"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yumlw7fbzbevvi2nz62kksdpwu" style="color: black;">International Journal of Reconfigurable Computing</a> </i> &nbsp;
The motion estimation is the most complex module in a video H.264/AVC encoder requiring a high processing throughput and high memory bandwidth, mainly when the focus is high definition videos.  ...  This special issue presents some of the latest developments in the area of design, specification, and modeling languages and applications of reconfigurable computing; reconfigurable architectures and novel  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2013/942021">doi:10.1155/2013/942021</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/7j6scjgtmbbxla64k7xpdifhbe">fatcat:7j6scjgtmbbxla64k7xpdifhbe</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200213200942/http://downloads.hindawi.com/journals/ijrc/2013/942021.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/d9/0e/d90e2483eaec28bdbe70bdc95e6d0b29a7919e70.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2013/942021"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> hindawi.com </button> </a>

High-level estimation and trade-off analysis for adaptive real-time systems

Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrholz, Philipp A. Hartmann, Wolfgang Nebel
<span title="">2009</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/t3x4vqewrncrfgn2wu7cafsbsq" style="color: black;">2009 IEEE International Symposium on Parallel &amp; Distributed Processing</a> </i> &nbsp;
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA.  ...  and reconfiguration times.  ...  Introduction This paper proposes a novel estimation method to be able to estimate the design costs for the implementation of adaptive applications with given throughput constraints on reconfigurable architectures  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ipdps.2009.5161208">doi:10.1109/ipdps.2009.5161208</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ipps/SanderZJHHN09.html">dblp:conf/ipps/SanderZJHHN09</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/c4cvi74rurelpnvnutdzgyxdue">fatcat:c4cvi74rurelpnvnutdzgyxdue</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170811164041/http://people.kth.se/~ingo/Papers/RAW2009-Estimation.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/0b/7b/0b7bf270b9d32fe0020553f7ce3bd13a2a49eddb.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ipdps.2009.5161208"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

PackeX: Low-Power High-Performance Packet Classifier Using Memory on FPGAs

Khalid Rehman, Zahid Ullah, Sungchang Lee
<span title="2021-06-07">2021</span> <i title="Hindawi Limited"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/6o4hgxplrbehxg4t53ub7zmfha" style="color: black;">Wireless Communications and Mobile Computing</a> </i> &nbsp;
In this work, we propose a novel high-speed packet classifier named as PackeX that enables the network to receive and forward the data packets in a simplest structure.  ...  A size of 128-rule 32-bit is successfully implemented on Xilinx Virtex-7 FPGA.  ...  On the other side, our proposed packet classifier uses a novel and simple architecture to develop the packet addresses into a TCAM that is partitioned to store in the distributed memory of the target FPGA  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2021/5544435">doi:10.1155/2021/5544435</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/hc4j3plq2nahxiz7xzwmxyipke">fatcat:hc4j3plq2nahxiz7xzwmxyipke</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20210715074712/https://downloads.hindawi.com/journals/wcmc/2021/5544435.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/7a/fc/7afc2d6552242da527e0af62ade94cc4e063f2d6.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2021/5544435"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> hindawi.com </button> </a>

A fuzzy logic based dynamic reconfiguration scheme for optimal energy and throughput in symmetric chip multiprocessors

Muhammad Yasir Qadri, Klaus D. McDonald-Maier
<span title="">2010</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/74wwkahd4bbfnlle2od7myqj4u" style="color: black;">2010 NASA/ESA Conference on Adaptive Hardware and Systems</a> </i> &nbsp;
This paper presents a novel coarse-grained reconfigurable symmetric chip multiprocessor (SCMP) architecture managed by a fuzzy logic engine that balances performance and energy consumption.  ...  With the advent of reconfigurable architectures it is now possible to support algorithms to find optimal solutions for an improved energy and throughput balance.  ...  In this paper a novel coarse-grained reconfigurable symmetric chip multiprocessor (SCMP) architecture is presented.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ahs.2010.5546239">doi:10.1109/ahs.2010.5546239</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ahs/QadriM10.html">dblp:conf/ahs/QadriM10</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/jba6t5io2bcqjig2lgdpg5xcda">fatcat:jba6t5io2bcqjig2lgdpg5xcda</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20201105090534/http://repository.essex.ac.uk/6849/1/A_fuzzy_logic_based_dynamic_reconfiguration_scheme.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/13/3b/133b594aca70a637800a9ff1445c1ecab0591e99.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ahs.2010.5546239"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems

Umar Minhas, Roger Woods, Georgios Karakonstantis
<span title="">2018</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/plojvu5mhreuxnue5ey7fivkbi" style="color: black;">2018 28th International Conference on Field Programmable Logic and Applications (FPL)</a> </i> &nbsp;
(FPGAs, GPUs, etc) using high-level heterogeneous programming environments.  ...  With FPGAs being increasingly integrated into existing software-based heterogeneous cloud environments, novel evaluation mechanisms are required to reveal the energyperformance trade-offs of accelerators  ...  heterogeneous cloud environments, novel evaluation mechanisms are required to reveal the energyperformance trade-offs of accelerators (FPGAs, GPUs, etc) using high-level heterogeneous programming environments  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/fpl.2018.00083">doi:10.1109/fpl.2018.00083</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/fpl/MinhasWK18.html">dblp:conf/fpl/MinhasWK18</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/z2hsqubwavax7ftepbqvurks7m">fatcat:z2hsqubwavax7ftepbqvurks7m</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200309191445/https://pureadmin.qub.ac.uk/ws/files/164065184/FPL2018.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e5/a0/e5a040a0c0ac5f1e904612c5dbe0f8ad751b8c84.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/fpl.2018.00083"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Hardware Accelerated SDR Platform for Adaptive Air Interfaces [article]

Tarik Kazaz, Christophe Van Praet, Merima Kulin, Pieter Willemen, Ingrid Moerman
<span title="2017-04-29">2017</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
The resulting system enables composition of reconfigurable air interfaces based on hardware/software co-processing on a single chip, allowing high processing throughput, at a smaller form factor and reduced  ...  proposed platform uses modern hybrid FPGA technology combined with novel ideas such as RF Network-on-Chip (RFNoC) and partial reconfiguration.  ...  Research Program on Internet of Things, the European Horizon 2020 Programmes under grant agreement n°645274 (WiSHFUL project) and n°671563 (Flex5Gware project), and the SBO SAMURAI project (Software Architecture  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1705.00115v1">arXiv:1705.00115v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/jqwyorvvijeu5kthvbeedinp6q">fatcat:jqwyorvvijeu5kthvbeedinp6q</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200914011228/https://arxiv.org/ftp/arxiv/papers/1705/1705.00115.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/88/1c/881c99bc81d1ffe3e02c2a6285df85f7e8c57398.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1705.00115v1" title="arxiv.org access"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> arxiv.org </button> </a>

Novel Cascade FPGA Accelerator for Support Vector Machines Classification

M. Papadonikolakis, C. Bouganis
<span title="">2012</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/j6amxna35bbs5p42wy5crllu2i" style="color: black;">IEEE Transactions on Neural Networks and Learning Systems</a> </i> &nbsp;
Furthermore, based on the special properties of the heterogeneous architecture, this paper introduces the first FPGA-oriented cascade SVM classifier scheme, which exploits the FPGA reconfigurability and  ...  This paper presents a fully scalable field programmable gate array (FPGA) architecture for the acceleration of SVM classification, which exploits the device heterogeneity and the dynamic range diversities  ...  Also, it was proven that a reconfigurable cascade scheme can switch from low-to high-precision classification and maintain the performance in high-levels, when the FPGA resource constraints do not allow  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tnnls.2012.2196446">doi:10.1109/tnnls.2012.2196446</a> <a target="_blank" rel="external noopener" href="https://www.ncbi.nlm.nih.gov/pubmed/24807131">pmid:24807131</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mpw73zegrbhr5pn7yvwhfu6bqq">fatcat:mpw73zegrbhr5pn7yvwhfu6bqq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809152152/http://cas.ee.ic.ac.uk/people/ccb98/papers/J_NovelCascadeFPGAAccelerator.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/08/5e/085e61e5ba0072677947d155b4e2994610e55001.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tnnls.2012.2196446"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor [chapter]

Emeka Mosanya, Christof Teuscher, Héctor Fabio Restrepo, Patrick Galley, Eduardo Sanchez
<span title="">1999</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
The CryptoBooster is a modular and reconfigurable cryptographic coprocessor that takes full advantage of current high-performance reconfigurable circuits (FPGAs) and their partial reconfigurability.  ...  The CryptoBooster works as a coprocessor with a host system in order to accelerate cryptographic operations. A series of cryptographic modules for different encryption algorithms are planned.  ...  Acknowledgments The CryptoBooster project is a joint project between the Swiss Federal Institute of Technology in Lausanne and Lightning Instrumentation SA, with funding from the Swiss Federal Office for  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-48059-5_21">doi:10.1007/3-540-48059-5_21</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/oabetf4tuzcp3ibwzgcq7yfpdm">fatcat:oabetf4tuzcp3ibwzgcq7yfpdm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20181030062125/https://link.springer.com/content/pdf/10.1007%2F3-540-48059-5_21.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/0d/c7/0dc7c3148c9ddc990097743d7f34cbf8c890fe43.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-48059-5_21"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

New Applications and Architectures Based on FPGA/SoC

Ignacio Bravo-Muñoz, Alfredo Gardel-Vicente, José Luis Lázaro-Galilea
<span title="2020-10-28">2020</span> <i title="MDPI AG"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ikdpfme5h5egvnwtvvtjrnntyy" style="color: black;">Electronics</a> </i> &nbsp;
The novel approach is based on an FPGA-CPU tester binding the advantages of reconfigurable hardware and software complexity through the CPU.  ...  The authors develop on an FPGA-based SmartNIC a reconfigurable pipeline for network processing.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/electronics9111789">doi:10.3390/electronics9111789</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/4vevl6enfzc6bhxscx5rujuzuq">fatcat:4vevl6enfzc6bhxscx5rujuzuq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20201031200207/https://res.mdpi.com/d_attachment/electronics/electronics-09-01789/article_deploy/electronics-09-01789.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e4/79/e479c68877027e0bbf129775875f415cbb8e961e.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/electronics9111789"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> mdpi.com </button> </a>
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