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A Novel High-Frequency PLL Design for wireless applications

Diary R. Sulaiman
2020 Journal of Electrical Systems  
This paper addresses a wide tuning range "2.4-5.0 GHz", novel high-frequency PLL design for wireless applications.  ...  The growing need in today's wireless applications is increasing requirements for identification of a high-speed low noise, low power novel Phase-locked loop (PLL) design.  ...  The key to design novelty is characterized by; lower phase noise, low jitter, low sensitivity to environmental changes, low power dissipation, and a wide PLL turnability over the chosen band of frequency  ... 
doaj:7a28141a2d6742eca35fd85a7d92dac2 fatcat:c4ushfqxo5ertjss6cyyhk43iq

Ultralow Timing Jitter 40-Gb/s Clock Recovery Using a Self-Starting Optoelectronic Oscillator

J. Lasri, P. Devgan, R. Tang, P. Kumar
2004 IEEE Photonics Technology Letters  
The oscillator simultaneously generates a 10-GHz-rate microwave signal and a train of 15-ps optical pulses with 40-fs timing jitter in the 100-Hz to 1-MHz range.  ...  Under direct optical-injection locking of the oscillator, we demonstrate simultaneous error-free extraction of both the electrical and the optical clocks of 10-GHz rate from either a single-channel 10-  ...  In this letter, we describe a new scheme to simultaneously extract both the electrical and the optical clocks of 10-GHz rate from either a single-channel 10-Gb/s return-to-zero (RZ) data stream or a four-channel  ... 
doi:10.1109/lpt.2003.819370 fatcat:m7mvqnskrjhh7gftak6by2qtji

Design and performance of the 6 GHz waveform digitizing chip DRS4

Stefan Ritt
2008 2008 IEEE Nuclear Science Symposium Conference Record  
An on-chip PLL ensures high timing accuracy over a wide temperature range.  ...  The high analog bandwidth of 850 MHz, low power consumption of 40 mW/channel and fast readout time make this chip attractive for many experiments, replacing traditional ADCs and TDCs.  ...  It is dead-band free in order to minimize the residual PLL jitter.  ... 
doi:10.1109/nssmic.2008.4774700 fatcat:6vizcs7l6fbxvnf6pswebayrjm

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

Mark Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Ben Parker, José A. Tierno, A. Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman
2013 IEEE Journal of Solid-State Circuits  
An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI.  ...  The PLL has a measured phase noise @10 MHz offset of 126.5 dBc/Hz at 20.1 GHz and 124.2 dBc/Hz at 24 GHz Index Terms-Bandwidth calibration, frequency synthesizers, phase locked loop, PLL.  ...  For example, a 20-26 GHz PLL followed by a frequency doubler has been proposed as a solution to generating the LO in a 60 GHz radio [1] .  ... 
doi:10.1109/jssc.2013.2239114 fatcat:saftb57xbnao3kmmf5gqjcw3xq

A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning

Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2006 IEEE Journal of Solid-State Circuits  
Fabricated in a 0.18-m CMOS process, the PLL occupies 0.15 mm 2 die area and achieves a frequency range of 0.5 to 2.5 GHz.  ...  This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes.  ...  ACKNOWLEDGMENT The authors thank National Semiconductor for providing IC fabrication, and particularly O. Norman for his sponsorship.  ... 
doi:10.1109/jssc.2006.884194 fatcat:bxs3kaduxfcbnc53su7jkh2z6e

SiGe BiCMOS integrated circuits for high-speed serial communication links

D. J. Friedman, M. Meghelli, B. D. Parker, J. Yang, H. A. Ainspan, A. V. Rylyakov, Y. H. Kwark, M. B. Ritter, L. Shan, S. J. Zier, M. Sorna, M. Soyuer
2003 IBM Journal of Research and Development  
Aspects focused on are the integration of 10 -13-Gb/s serializer/deserializer chips with subpicosecond jitter performance, the realization of 40 -56-Gb/s multiplexer/demultiplexer functions and clock-and-datarecovery  ...  SiGe BiCMOS integrated circuits for highspeed serial communication links Considerable progress has been made in integrating multi-Gb/s functions into silicon chips for data-and telecommunication applications  ...  Acknowledgment The authors wish to acknowledge the SiGe technology group of the IBM Microelectronics Division for chip fabrication. They also wish to thank K. Jenkins, D. Heidel  ... 
doi:10.1147/rd.472.0259 fatcat:xsqocvb2fbf4rg32auvoowwply

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

Wanghua Wu, Robert Bogdan Staszewski, John R. Long
2014 IEEE Journal of Solid-State Circuits  
rms for a 62 GHz carrier with 1.22 GHz bandwidth.  ...  The fractional-N ADPLL employs a high-resolution 60 GHz digitallycontrolled oscillator (DCO) and is capable of multi-rate two-point FM.  ...  Straver, A. Akhnoukh, and M. Spirito for measurement support. They also thank Integrand Software for providing the EM simulation tool, EMX.  ... 
doi:10.1109/jssc.2014.2301764 fatcat:rlafztretzdslovw46qwr263oa

Experimental Missions in W-Band: A Small LEO Satellite Approach

M. Lucente, T. Rossi, A. Jebril, M. Ruggieri, S. Pulitano, A. Iera, A. Molinaro, C. Sacchi, L. Zuliani
2008 IEEE Systems Journal  
W-band (75-110 GHz) is proposed nowadays as a valuable alternative to intensively-exploited Ku and Ka bands for high-speed transmission over satellite networks.  ...  In such a perspective, IKNOW should be regarded as a "pilot mission", whose results will be used for a first uplink-downlink satellite channel characterization, in-orbit validation of W-band technology  ...  ACKNOWLEDGEMENTS Authors wish to thanks Giorgio Perrotta of IMT S.r.l. and dr. Mirko Albani, dr. Giuseppe Codispoti of Italian Space Agency (ASI) for their useful review and suggestions.  ... 
doi:10.1109/jsyst.2007.914787 fatcat:36rtj67rd5bqffleb7ige4xaum

Clock-centric Serial Links for the Synchronization of Distributed Readout Systems

D. Calvet
2020 IEEE Transactions on Nuclear Science  
Often, this hardware has to be synchronized to a common reference clock with minimal skew and low jitter.  ...  This work reports some first steps to explore a third scheme for clock and synchronous message distribution.  ...  Additional skew and jitter are incurred by the Flip-Flop layer, but this can be very small, e.g. 200 ps typical delay and 0.8 ps rms maximum additive jitter for ON Semiconductor NB7V52M 10 GHz differential  ... 
doi:10.1109/tns.2020.3006698 fatcat:mn4aws5rxnbf7n5lbqqxivvz5u

640-Gbit/s Data Transmission and Clock Recovery Using an Ultrafast Periodically Poled Lithium Niobate Device

L.K. Oxenlwe, F. Gomez, C. Ware, S. Kurimura, H.C.H. Mulvad, M. Galili, H. Nakajima, J. Ichikawa, D. Erasme, A.T. Clausen, P. Jeppesen
2009 Journal of Lightwave Technology  
The reason for the low jitter values is a very low-noise VCO and the low bandwidth of the PLL.  ...  The ERGO laser itself has very low jitter and a quite low PLL bandwidth of 20 kHz.  ...  His doctoral work has been focused on creating stable fiberbased switches and switches for 640-Gbit/s add/drop multiplexing.  ... 
doi:10.1109/jlt.2008.2009322 fatcat:4jid2iwyongv3ixtmgmwhpy5yi

3G: The Evolution of the Serial Digital Interface (SDI)

John Hudson, Nigel Seth-Smith
2006 SMPTE Motion Imaging Journal  
their products are typically character- ized and tested beyond 3 GHz and easily meet the SMPTE 424M requirement of greater than 10 dB at 3 GHz with significant margin.  ...  10 dB between 1.485 GHz and 3 GHz and better than 15 dB from 5 Mhz to 1.485 GHz.  ... 
doi:10.5594/j16131 fatcat:faw5qrfndbc6td5rilpfgivobu

Distributed Waveform Generator: A New Circuit Technique for Ultra-Wideband Pulse Generation, Shaping and Modulation

Yunliang Zhu, Jonathan D. Zuegel, John R. Marciante, Hui Wu
2009 IEEE Journal of Solid-State Circuits  
A new circuit technique, the distributed waveform generator (DWG), is proposed for low-power ultra-wideband pulse generation, shaping and modulation.  ...  A 10-tap, 10 GSample/s, single-polarity DWG prototype achieves a pulse rate of 1 GHz while consuming 50 mW, and demonstrates OOK modulation using 16 Mb/s PRBS data.  ...  Chatterjee, A. Bahai, P. Holloway, M. Bohsali, J. Yu, A. Shah, V. Abellera, P. Misich, and J. Wan of National Semiconductor for their support in chip fabrication.  ... 
doi:10.1109/jssc.2009.2013770 fatcat:cfwq7tvxc5hwfpkmhyyn2l2ok4

Program

2021 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
A replica-based automatic tuning scheme is introduced to achieve a very wide frequency range without the need for manual tuning, while also increasing the sensitivity and minimizing the additive jitter  ...  Fabricated in a mainstream 40-nm technology, the PLL is characterized, showing a reference spur level of -108.3 dBc and a fractional spur under -95.0 dBc.  ...  And the last talk introduces a new low cost reference clock generation method, molecular clock, for wireless network synchronization and navigation. Speakers Speakers: 1.  ... 
doi:10.1109/rfic51843.2021.9490449 fatcat:wmoshjhq3nhxxljgu46qup325u

FPGA-based electronic system for the control and readout of superconducting quantum processors [article]

Y. Yang, Z. Shen, X. Zhu, Z. Wang, G. Zhang, J. Zhou, X. Jiang, C. Deng, S. Liu
2022 arXiv   pre-print
With the rapid development of superconducting quantum circuit (SQC) technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems.  ...  Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors.  ...  TESTING In this section, we present the test results of the electronic system. A. Jitter of the electronic system We usually use skew and jitter to characterize the synchronization of the system.  ... 
arXiv:2110.07965v2 fatcat:rv5safxlsvdgjefigxuzr3i4xm

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott Reynolds, Xin Li, Larry Pileggi (+3 others)
2013 IEEE Journal of Solid-State Circuits  
Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%.  ...  The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier.  ...  A Linearized, Low-Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing I.  ... 
doi:10.1109/jssc.2013.2252513 fatcat:acagot7kirdy5gc2ptrsqmcru4
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