Filters








4,040 Hits in 5.7 sec

The twin-transistor noise-tolerant dynamic circuit technique

G. Balamurugan, N.R. Shanbhag
2001 IEEE Journal of Solid-State Circuits  
This paper describes a new circuit technique for designing noise-tolerant dynamic logic.  ...  It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design.  ...  Section III briefly reviews existing techniques for noise-tolerant dynamic circuit design. In Section IV, a new noise-tolerant circuit technique is described.  ... 
doi:10.1109/4.902768 fatcat:45u3gmc33fgxzb5hm3sxgwpxw4

An energy-efficient noise-tolerant dynamic circuit technique

N.R. Shanbhag, L. Wang
2000 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
To address this problem, a new noise-tolerant dynamic circuit technique is presented.  ...  Index Terms-ASIC, deep submicron noise, dynamic circuits, noise immunity, noise-tolerant circuits.  ...  MIRROR TECHNIQUE: A NEW NOISE-TOLERANT DYNAMIC CIRCUIT TECHNIQUE In Section III-A, we present an energy-efficient noise-tolerant dynamic circuit technique referred to as the mirror technique.  ... 
doi:10.1109/82.885137 fatcat:ezkbtikhrze2fcw4scukrxzmpe

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

Yun Chiu, P.R. Gray, B. Nikolic
2004 IEEE Journal of Solid-State Circuits  
A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gain-boosting technique is described.  ...  Prototyped in a 0.18m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration  ...  Wang for improving the manuscript are also acknowledged.  ... 
doi:10.1109/jssc.2004.836232 fatcat:wmpuk7crqzht7intpvx6rggbf4

SVX4: a new deep submicron readout IC for the Tevatron Collider at Fermilab

B. Krieger, S. Alfonsi, N. Bacchetta, S. Centro, L. Christofek, M. Garcia-Sciveres, C. Haber, K. Hanagaki, J. Hoff, M. Johnson, H. von der Lippe, E. Mandelli (+12 others)
2003 2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515)  
SVX4 is the new silicon strip readout IC designed to meet the increased radiation tolerance requirements for Run IIb at the Tevatron collider.  ...  Unlike its predecessors, the new design also includes the necessary features required for generic use by both the CDF and D0 experiments at Fermilab.  ...  Additionally, we thank Alex Grillo, Gunther Haller, and Helmuth Spieler for their valuable contributions to our design reviews, and Academia Sinica, Taiwan, for assistance with the pre-production fabrication  ... 
doi:10.1109/nssmic.2003.1352072 fatcat:2rvcldlybvajfesufuox4xrkde

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

Jipeng Li, Un-Ku Moon
2004 IEEE Journal of Solid-State Circuits  
A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC.  ...  Fabricated in a 0.18m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm 2 of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100 MS/s.  ...  Min at National Semiconductor for their helpful technical advice, and National Semiconductor for providing fabrication of the prototype IC.  ... 
doi:10.1109/jssc.2004.829378 fatcat:jntnzn3tmfgutet37wwqugpple

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

Mahmut E. Sinangil, Marcus Yip, Masood Qazi, Rahul Rithe, Joyce Kwong, Anantha P. Chandrakasan
2012 IEEE Transactions on Circuits and Systems - II - Express Briefs  
This paper covers the main building blocks of a system implementation including digital logic, embedded memories and analog-to-digital conversion and describes the challenges and solutions to designing  ...  these blocks for low-voltage operation.  ...  For example, highly-digital pipelined ADCs using comparator-based switched-capacitor circuits and zero-crossing detectors eliminate the need for op-amps, making low-voltage pipelined ADCs a promising new  ... 
doi:10.1109/tcsii.2012.2208675 fatcat:b25ubotnpvd3tkhrzbhuwe4s4i

A Range-Scaled 13b 100 MS/s 0.13 um CMOS SHA-Free ADC Based on a Single Reference

Dong-Hyun Hwang, Jung-Eun Song, Sang-Pil Nam, Hyo-Jin Kim, Tai-Ji An, Kwang-Soo Kim, Seung-Hoon Lee
2013 JSTS Journal of Semiconductor Technology and Science  
This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems.  ...  The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively.  ...  CIRCUIT IMPLEMENTATION MDAC1 for the Proposed Range-Scaling Technique In conventional pipeline ADCs with the same signal range for input and reference voltages, for example, a 3b MDAC1 commonly amplifies  ... 
doi:10.5573/jsts.2013.13.2.98 fatcat:tob2epkdkbckfgg6stb3eeum4m

Session 15 overview: Data-converter techniques: Data converters subcommittee

Seung-Tak Ryu, Matt Straayer
2015 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers  
Papers in this session include highperformance continuous-time delta-sigma ADCs, a PVT-insensitive TDC implemented in 14nm FinFET technology, and new buffering techniques for both reference voltages and  ...  noise to below -60dBFS, allowing for a very small area and power-efficient implementation.  ...  Papers in this session include highperformance continuous-time delta-sigma ADCs, a PVT-insensitive TDC implemented in 14nm FinFET technology, and new buffering techniques for both reference voltages and  ... 
doi:10.1109/isscc.2015.7063030 dblp:conf/isscc/RyuS15 fatcat:dt62rxbplnd4takba25ecc5s3a

A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages

Jin-Fu LIN, Soon-Jyh CHANG
2011 IEICE transactions on electronics  
In this paper, two techniques for implementing a lowpower pipelined analog-to-digital converter (ADC) are proposed.  ...  The ADC achieves a spurious free dynamic range (SFDR) of 62.15 dB and a signal-to-noise distortion ratio (SNDR) of 50.85-dB for 2-MHz input frequency at a 100-MS/s sampling rate.  ...  Fortunately, with the help of the digital error correction technique, a pipelined ADC can tolerate large offset.  ... 
doi:10.1587/transele.e94.c.89 fatcat:o5qojaulozempfeadozgn6czzy

Introduction to the Special Issue on the IEEE 2003 Custom Integrated Circuits Conference

E. Charbon, A.Z.H. Wang, S. Natarajan
2004 IEEE Journal of Solid-State Circuits  
Nanua and Blaauw address the PD SOI noise issues in a paper entitled "Noise Analysis Methodology for Partially Depleted SOI Circuits" and present a noise model to account for the floating body and the  ...  ., describes a new leakage current reduction methodology for realizing statistical leakage current reduction using a time locality of activation probability of a circuit block.  ...  He is a Guest Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS for the CICC 2003 and ISSCC 2004  ... 
doi:10.1109/jssc.2004.832197 fatcat:z7qvqqxgmbdbzaouoz2u3dj7za

A Domain Extension Algorithm for Digital Error Correction of Pipeline ADCs

Ting Li, Chao You
2014 Circuits and Systems  
This new approach also promises significant improvements to the spurious-free dynamic range (SFDR), the total harmonic distortion (THD), the signal-to-noise ratio (SNR) and the minor analog and digital  ...  A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain  ...  In this paper, a new algorithm is developed to improve the comparator offset correction ability for the 1.5-bit/stage pipeline ADC.  ... 
doi:10.4236/cs.2014.52006 fatcat:lx5fthga55btvmqucjrrcpzzym

Low swing dual threshold voltage domino logic

Volkan Kursun, Eby G. Friedman
2002 Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02  
A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity.  ...  With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% while improving the noise immunity by 2.6% as compared to standard domino logic circuits.  ...  Simulation Results The SDK, LSDFDK, and LSDWDK circuit techniques are evaluated for a three stage pipeline (see Fig. 3 ) composed of four input AND gates assuming a 0.18 µm CMOS technology.  ... 
doi:10.1145/505306.505317 dblp:conf/glvlsi/KursunF02 fatcat:fmcgflebencrrofvbcujk3pemm

Low swing dual threshold voltage domino logic

Volkan Kursun, Eby G. Friedman
2002 Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02  
A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity.  ...  With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% while improving the noise immunity by 2.6% as compared to standard domino logic circuits.  ...  Simulation Results The SDK, LSDFDK, and LSDWDK circuit techniques are evaluated for a three stage pipeline (see Fig. 3 ) composed of four input AND gates assuming a 0.18 µm CMOS technology.  ... 
doi:10.1145/505312.505317 fatcat:orbt3fcj2vhujknskve4eoag7y

FOREWORD

Minoru FUJISHIMA
2017 IEICE transactions on electronics  
The second paper proposes a logarithmic compression technique for analog-to-digital converters and achieves wide dynamic range. Other two papers demonstrate low phase noise oscillator designs.  ...  For coordinate rotational digital computer (CORDIC), a parallel pipeline architecture is shown.  ... 
doi:10.1587/transele.e100.c.348 fatcat:tn4douvjrracxjyzpjqjq7vyvq

Reliable Systems on Unreliable Fabrics

Todd Austin, Valeria Bertacco, Scott Mahlke, Yu Cao
2008 IEEE Design & Test of Computers  
on a commercial CMP based on Sun's Niagara, the technique provided defect tolerance for 99.2% of the chip area with only a 5.8% area overhead.  ...  To further explore design techniques for circuit reliability, the Resilient-System Design Team will implement these degradation models in circuit simulation tools to diagnose their impact on dynamic and  ... 
doi:10.1109/mdt.2008.107 fatcat:ykmurvstufcvrevyigxcyp2qhu
« Previous Showing results 1 — 15 out of 4,040 results